A method for quasi-cyclic low-density parity-check (QC-LDPC) encoding and decoding of a data packet by a lifted matrix is provided, the method comprising: lifting the QC-LDPC code for maximal code length N.sub.max and maximal circulant size Z.sub.upper of the base matrix; generating a plurality of optimal values r.sub.i for a plurality of circulants Z.sub.1, Z.sub.2, . . . , Z.sub.upper based on the QC-LDPC code lifted for maximal length N.sub.max, 0r.sub.iZ.sub.upper1; saving the generated plurality of optimal values r.sub.i corresponding to the plurality of circulants Z.sub.1, Z.sub.2, . . . , Z.sub.upper and a matrix for the QC-LDPC code lifted for maximal length N.sub.max in the memory; receiving a current circulant Z.sub.current from the plurality of circulants Z.sub.1, Z.sub.2, . . . , Z.sub.upper; selecting a current optimal value r.sub.current from the plurality of optimal values r.sub.i stored in the memory corresponding to the current circulant Z.sub.current; and lifting the base matrix based on the current optimal value r.sub.current.

Aspects of the present disclosure relate to low density parity check (LDPC) encoding. At least a portion of the parity bits generated by an LDPC encoder for an initial transmission may be stored for use in generating subsequent hybrid automatic repeat request (HARQ) redundancy versions. In some examples, at least the degree-two and degree-three parity bits included in the initial transmission may be stored. The parity bits may be stored within a layer 2 (L2) or an upper layer buffer or within the LDPC encoder. For example, the parity bits may be stored within the HARQ buffer.

Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.

A low-density parity check (LDPC) decoder may include a variable node processing unit and a check node processing unit. The check node processing unit includes memory elements storing a check node value. The memory elements are interconnected through two or more paths, and each of the paths may include a total or partial cyclic permutation of the memory elements to transmit the check node value.

A quasi-cyclic low density parity check (QC LDPC) code rate matching method is disclosed. According to the rate matching method in the present disclosure, the minimum lifting value can be selected from among lifting values by which a codeword longer than a target code block can be generated. A coding gain through retransmission can be acquired by generating the codeword that is longer than the target code block. In addition, by selecting a lifting value of a proper magnitude, rate matching for information bit sequences of various lengths can be performed.

The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size.

Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.

A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

This application provides an LDPC code encoding method and a communication apparatus, to meet a requirement of increasing redundant bits through retransmission in an IR-HARQ mechanism, so as to decrease a channel coding rate, and improve decoding performance of an LDPC code. In the method, a check matrix of the LDPC code is used as a basic matrix, and the basic matrix is extended to obtain a mother matrix compatible with a plurality of code rates. During LDPC encoding, a transmit device reads, from the mother matrix, a check matrix corresponding to a required code rate, and performs LDPC encoding on an information bit sequence based on the read check matrix. LDPC encoding is performed on the information bit sequence by using check matrices of different sizes, to obtain different quantities of redundant bits.