H04L2025/03477

HIGH-SPEED RECEIVER ARCHITECTURE

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Electrical dispersion compensator and tap coefficient calculation method suitably applicable thereto
09596107 · 2017-03-14 · ·

There is provided an apparatus allowing waveform shaping even at a low sampling rate, which includes a sampling unit, an equalizing unit, a tap coefficient calculating unit, a delay adjusting unit, a peak monitoring unit, and a timing value extracting unit. The timing value extracting unit provides a magnitude of a delay to the delay adjusting unit, and from a plurality of sets of the magnitude of the delay provided by the delay adjusting unit and maximum values of output signal intensity acquired by the peak monitoring unit, acquires the magnitude of a delay where the output signal intensity becomes the greatest, as a suitable delay amount, and notifies the delay adjusting unit of the suitable delay amount.