H04L2025/03484

CTLE gear shifting to enable CDR frequency lock in wired communication

A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

RECEIVER RECEIVING DATA SIGNAL OF MULTI-LEVEL AND ELECTRONIC SYSTEM INCLUDING THE SAME

A receiver includes a first decision feedback equalization (DFE) circuit configured to receive a first multi-level data signal, and output a first bit correction signal correcting a level of the first multi-level data signal based on first bit data of a second multi-level data signal received before the first multi-level data signal, a second DFE circuit configured to output a DFE signal based on second bit data of the second multi-level data signal and levels of data signals received before the second multi-level data signal, and a slicer configured to determine first bit data of the first multi-level data signal based on a level of the first bit correction signal, and correct the level of the first bit correction signal with a second bit correction signal based on the DFE signal.