An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

An apparatus for equalizing a digital input signal is provided. The apparatus includes an input node configured to receive the digital input signal. Further, the apparatus includes a plurality of filters coupled in parallel to the input node. The plurality of filters are configured to filter the digital input signal and generate a respective filtered signal. Additionally, the apparatus includes a combiner circuit coupled to the plurality of filters. The combiner circuit is configured to receive the respective filtered signal from the plurality of filters, and to generate an equalized signal by combining the received filtered signals according to a non-linear equalization function.

An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.

A method of blind tap coefficient adaptation includes receiving a digital data signal including random digital data, equalizing a first portion of the digital data signal using a first set of predetermined tap coefficients and a second portion of the digital data signal using a second set of predetermined tap coefficients. The method includes generating a first eye diagram and a second eye diagram from a first portion and a second portion of an equalized signal, respectively. The first eye diagram is compared with the second eye diagram to determine which of the sets of predetermined tap coefficients results in a data signal having a higher signal quality. The method includes inputting to an equalizer as an initial set of tap coefficients the first set of predetermined tap coefficients or the second set of predetermined tap coefficients according to the determination.