Various embodiments described herein relate to methods and apparatus for etching a semiconductor substrate to remove a target material from a surface of the substrate. Generally, the techniques described herein are thermal techniques that do not rely on the use of plasma. In a number of embodiments, a particular gas mixture is provided to the reaction chamber to react with the target material. The gas mixture may include a combination of a halogen source such as hydrogen fluoride (HF), an organic solvent and/or water, an additive, and a carrier gas. A number of different materials may be used for the organic solvent and/or for the additive.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A method and apparatus for growing an oxide layer within a feature of a substrate is described herein. The method is suitable for use in semiconductor manufacturing. The oxide layer is formed by exposing a substrate to both a high pressure oxidant exposure and a lower pressure oxygen containing plasma exposure. The high pressure oxidant exposure is performed at a pressure of greater than 10 Torr, while the lower pressure oxygen containing plasma exposure is performed at a pressure of less than about 10 Torr. The features are high-aspect ratio trenches or holes within a stack of silicon oxide and silicon nitride layers.

There is provided a method of manufacturing a semiconductor device, which includes: forming a silicon film inside a recess formed in a surface of a workpiece by supplying a film forming gas containing silicon to the workpiece; subsequently, supplying a process gas, which includes a halogen gas for etching the silicon film and a roughness suppressing gas for suppressing roughening of a surface of the silicon film after being etched by the halogen gas, to the workpiece; etching the silicon film formed on a side wall of the recess to enlarge an opening width of the recess by applying thermal energy to the process gas and activating the process gas; and subsequently, filling silicon into the recess by supplying the film forming gas to the workpiece and depositing silicon on the silicon film remaining in the recess.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion, and the first dielectric layer is a single-layer structure. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.

In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

A system and method for treating a substrate in a reaction chamber. A transfer chamber is arranged between a first lock and a second lock, wherein the second lock is provided between the transfer chamber and the reaction chamber. A substrate is transferred into the transfer chamber through the first lock, and the first lock is closed. In a next step, the transfer chamber is flooded with the same gas as in the reaction chamber and the pressure and temperature of the gaseous atmosphere in the transfer chamber is controlled to be the same as in the reaction chamber. Then, the second lock is opened and the substrate is transferred from the transfer chamber into the reaction chamber to treat the substrate. A computer program product for carrying out the above method.

A SiO.sub.2 layer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfO.sub.2 layer 11b is disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfO.sub.2 layer. P.sup.+ layers are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides of the semiconductor fin, a gate dielectric layer on a surface of the semiconductor fin above the isolation regions, and a gate on a part of the gate dielectric layer; and performing threshold voltage adjustment ion implantation on a part of the semiconductor fin that is not covered by the gate, so as to enable implanted impurities to diffuse into a part of the semiconductor fin that is covered by the gate. Forms of the present disclosure can reduce loss of impurities implanted by the threshold voltage adjustment ion implantation.