A method for manufacturing a semiconductor includes: providing a substrate; forming a polysilicon layer on the substrate, a surface, away from the substrate, of the polysilicon layer having a native oxide; and performing a nitriding treatment to the native oxide, to nitrogenize the native oxide into a silicon oxynitride layer. The native oxide is nitrogenized into the silicon oxynitride layer.

A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.

A method of manufacturing a semiconductor device, includes forming a film containing a predetermined element on a substrate by supplying a precursor containing the predetermined element to the substrate having a first temperature in a process chamber, changing a temperature of the substrate to a second temperature higher than the first temperature under an atmosphere containing a first oxygen-containing gas in the process chamber, and oxidizing the film while maintaining the temperature of the substrate at the second temperature under an atmosphere containing a second oxygen-containing gas in the process chamber.

According to one embodiment, a substrate processing method includes providing a substrate containing Si raised features, depositing a conformal film on the Si raised features, and performing a spacer etch process that removes horizontal portions of the conformal film while substantially leaving vertical portions of the conformal film to form sidewall spacers on the Si raised features, the performing including a) exposing the substrate to a plasma-excited first process gas consisting of H.sub.2 gas and optionally an inert gas, and b) exposing the substrate to a plasma-excited second process gas containing i) NF.sub.3, O.sub.2, H.sub.2, and Ar, ii) NF.sub.3, O.sub.2, and H.sub.2, iii) NF.sub.3 and O.sub.2, NF.sub.3, O.sub.2, and Ar, iv) NF.sub.3 and H.sub.2, or v) NF.sub.3, H.sub.2, and Ar. The method further includes removing the Si raised features while maintaining the sidewall spacers on the substrate. The removing may be performed using steps a) and b).

A method of manufacturing a semiconductor device includes forming a thin film having excellent etching resistance and a low dielectric constant on a substrate, removing first impurities containing H.sub.2O and Cl from the thin film by heating the thin film at a first temperature higher than a temperature of the substrate in the forming of the thin film, and removing second impurities containing a hydrocarbon compound (C.sub.xH.sub.y-based impurities) from the thin film in which heat treatment is performed at the first temperature by heating the thin film at a second temperature equal to or higher than the first temperature.

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

A method for forming a thermal oxide film on a semiconductor substrate, including: a correlation acquisition step of providing a plurality of semiconductor substrates; a substrate cleaning step of cleaning a semiconductor substrate; a thermal oxide film thickness estimation step of determining a constitution of a chemical oxide film formed on the semiconductor substrate by the cleaning in the substrate cleaning step and, based on the correlation, estimating a thickness of a thermal oxide film on a hypothesis that the semiconductor substrate has been subjected to a thermal oxidization treatment conditions in the correlation acquisition step; a thermal oxidization treatment condition determination step of determining thermal oxidization treatment conditions based on the thermal oxidization treatment conditions in the correlation acquisition step so that the thermal oxide film is a predetermined thickness; and a thermal oxide film formation step of forming a thermal oxide film on the semiconductor substrate.

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.