A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.

A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.

A three-dimensional stacked memory device provides uniform programming speeds for a block of memory cells. The channel layers of the memory strings which are relatively close to a local interconnect of a stack are doped to account for a reduced blocking oxide thickness. Channel layers of remaining memory strings are undoped. The doping can be performing by masking the channel layers which are to remain undoped while exposing the other memory holes to a dopant. The dopant can be provided, e.g., in a carrier gas, spin on glass or other solid, or by plasma doping. An n-type dopant such as antimony, arsenic or phosphorus may be used. Heating causes the dopants to diffuse into the channel layer. Another approach deposits doped silicon for some of the channel layers and undoped silicon for other channel layers.

A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

A diffusing agent composition that can efficiently form a thin film in which an impurity diffusion component can be diffused into a semiconductor substrate at a higher concentration than a conventional one and a method of manufacturing a semiconductor substrate using the diffusing agent composition. The diffusing agent composition includes an impurity diffusion component and a silane coupling agent the silane coupling agent including a group which generates a silanol group by hydrolysis and alkyl groups and at least one of the alkyl groups includes, in a chain and/or at an end, at least one amino group selected from a primary amino group, a secondary amino group and a tertiary amino group.

The invention relates to a method for doping semiconductor substrates by means of a co-diffusion process. First, semiconductor substrates are coated at least on one side with a layer containing at least one first dopant. Two of said substrates in each case are arranged in a process chamber in such a way that two of the coated sides thereof are brought in direct contact.

A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.