Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.

In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.

In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.

A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.