A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A ferroelectric material is arranged over the substrate and laterally between the first doped region and the second doped region. A conductive electrode is over the ferroelectric material and between sidewalls of the ferroelectric material. One or more sidewall spacers are arranged along opposing sides of the ferroelectric material. A dielectric layer continuously and laterally extends from directly below the one or more sidewall spacers to directly below the ferroelectric material.

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first doped region and a second doped region disposed within a substrate. A ferroelectric material is arranged over the substrate and between the first doped region and the second doped region. An isolation structure is arranged within the substrate along a first side of the ferroelectric material. The isolation structure has a first width measured along an uppermost surface of the isolation structure and a second width measured along a horizontal line below the uppermost surface of the isolation structure. The second width is larger than the first width.

A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

A semiconductor device includes a metal layer and a spacer arranged adjacent to the metal layer. The spacer includes a composite-dielectric layer including a composite-dielectric material. A composition of the composite-dielectric material is a mixture of a composition of a first dielectric material and a composition of a second dielectric material different from the first dielectric material.

A method for manufacturing a semiconductor device includes steps of forming a protective film on a semiconductor substrate, forming a resist film on the protective film such that the resist film includes a region where the resist film becomes thicker from a drain electrode to a source electrode, forming a first opening in the resist film by irradiating the resist film in the region with an electron beam and developing the resist film, forming a second opening that exposes an upper surface of the semiconductor substrate by removing the protective film using the resist film in which the first opening is formed as a mask, forming a third opening in the resist film by further developing the resist film after forming the second opening, the third opening being formed by expanding the first opening toward the drain electrode, and forming a gate electrode in the second and the third openings.

A method for forming a semiconductor device includes forming a metal layer and a spacer adjacent to the metal layer. The spacer includes a composite-dielectric layer including a composite-dielectric material. A composition of the composite-dielectric material is a mixture of a composition of a first dielectric material and a composition of a second dielectric material different from the first dielectric material.

Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.

Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.