A method for making a MOSFET includes forming a gate oxide layer on a substrate; depositing and forming a polysilicon layer on the gate oxide layer; removing the polysilicon layer and the gate oxide layer in a target area by means of dry etching. The remaining gate oxide layer forms a gate oxide of the MOSFET. The remaining polysilicon layer forms a gate of the MOSFET. The method further includes performing LDD implantation on the substrate at both sides of the gate, to form a first LDD area and a second LDD area respectively; and performing SD implantation to form a source and a drain in the substrate at both sides of the gate respectively. Before one of the steps after the depositing and forming a polysilicon layer on the gate oxide layer, fluorine ion implantation is performed.

A method for fabricating a semiconductor device includes: forming a gate structure including a source side and a drain side over a substrate, wherein a dielectric material and a columnar crystal grain material are stacked over the substrate; doping a chemical species on the drain side of the gate structure; and exposing the gate structure doped with the chemical species to a re-growth process in order to thicken the dielectric material on the drain side of the gate structure.

A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

The present disclosure provides a semiconductor device, including a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer between the metal gate layer and the substrate, wherein the ferroelectric layer is configured to cause a strain in the channel when applied with an electrical field.

A method is presented for tuning work functions of transistors. The method includes forming a work function stack over a semiconductor substrate, depositing a germanium oxide layer and a barrier layer over the work function stack, and annealing the germanium oxide layer to desorb oxygen therefrom to trigger oxidation of at least one conducting layer of the work function stack. The work function stack includes three layers, that is, a first layer being a TiN layer, a second layer being a titanium aluminum carbon (TiAlC) layer, and a third layer being a second TiN layer.

In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.

A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device.

Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure over a substrate and forming a sealing layer surrounding the dummy gate structure. The method includes forming a spacer covering the sealing layer and removing the dummy gate structure to form a trench. The method further includes forming an interfacial layer and a gate dielectric layer. The method further includes forming a capping layer over the gate dielectric layer and partially oxidizing the capping layer to form a capping oxide layer. The method further includes forming a work function metal layer over the capping oxide layer and forming a gate electrode layer over the work function metal layer. In addition, a bottom surface of the capping oxide layer is higher than a bottom surface of the spacer.

A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.