A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer is between the work function layer and the substrate, the work function layer is between the first dielectric layer and the gate electrode, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion. The semiconductor device structure includes. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.

A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.

A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T.sub.1 of the cap portion is greater than a thickness T.sub.2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

A method includes depositing a first high-k dielectric layer over a first semiconductor region, performing a first annealing process on the first high-k dielectric layer, depositing a second high-k dielectric layer over the first high-k dielectric layer; and performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer.

Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

A method includes providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium. The method further includes forming a metal nitride layer over the high-k gate dielectric layer and performing a first treatment to the structure using a metal-containing gas. After the performing of the first treatment, the method further includes depositing a silicon layer over the metal nitride layer; and then annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer. The metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas.

A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.