Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

The present disclosure provides a semiconductor device including a substrate, a gate structure formed over the substrate, the gate structure including a first ferroelectric material having a first remanent polarization and a second ferroelectric material having a second remanent polarization, the first remanent polarization being smaller than the second remanent polarization, and source and drain regions formed in the substrate, the source and drain regions being laterally separated by a channel region extending along a length direction below the gate structure, wherein the first ferroelectric material and the second ferroelectric material are stacked in a plane parallel to an upper surface of the substrate.

A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure.

Provided are a film structure including hafnium oxide, an electronic device including the same, and a method of manufacturing the same. The film structure including hafnium oxide includes a hafnium oxide layer including hafnium oxide crystallized in a tetragonal phase, and first and second stressor layers apart from each other with the hafnium oxide layer therebetween and applying compressive stress to the hafnium oxide layer.

An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

A transistor includes a substrate and a gate over the substrate. The transistor further includes a source and a drain over the substrate on opposite sides of the gate. The transistor further includes a channel region beneath the gate separating the source from the drain, the channel region having a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The transistor further includes a silicide over a first portion of the drain, wherein a second portion of the drain, closer to the gate than the first portion, is an unsilicided region.

A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H.sub.2O.sub.2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.

A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a channel region and a gate structure surrounding the channel region, each gate structure having a phase-changed high-k gate dielectric layer lining a gate trench thereof, the gate trench defined by a pair of spacers. The semiconductor structure further includes a conformal dielectric capping layer over each phase-changed high-k gate dielectric layer, the conformal dielectric capping layer having a higher dielectric constant than the phase-changed high-k gate dielectric layer. Further included on the n-type FinFETs is a multi-layer replacement gate stack of n-type work function material over the phase-changed high-k gate dielectric layer. A method of fabricating the semiconductor structure is also provided.

Embodiments of the present disclosure generally relate to methods for forming a high-k gate dielectric in a transistor. The high-k gate dielectric may be formed by introducing a fluorine containing gas into a processing chamber during the deposition of the high-k gate dielectric in the processing chamber. In one embodiment, the high-k gate dielectric is formed by an ALD process in a processing chamber, and a fluorine containing gas is introduced into the processing chamber during one or more stages of the ALD process. Fluorine ions, molecules or radicals from the fluorine containing gas (may be activated by a plasma) can fill the oxygen vacancies in the high-k dielectric.