Patent classifications
H01L21/28194
Low-k feature formation processes and structures formed thereby
Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.
Transistor gate structure with hybrid stacks of dielectric material
An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.
EPITAXIAL STRONTIUM TITANATE ON SILICON
A method for processing a substrate includes positioning a silicon substrate in a deposition chamber. One or more intermediate layers are deposited on a surface of the silicon. The one or more intermediate layers can include strontium, which combines with the silicon to form strontium silicide. Alternatively, the one or more intermediate layers comprise germanium. A layer of amorphous strontium titanate is deposited on the one or more intermediate layers in a transient environment in which oxygen pressure is reduced while temperature is increased. The substrate is then exposed to an oxidizing and annealing atmosphere that oxidizes the one or more intermediate layers and converts the layer of amorphous strontium titanate to crystalline strontium titanate.
MATERIAL HAVING SINGLE CRYSTAL PEROVSKITE, DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.
SEMICONDUCTOR MANUFACTURING APPARATUS
A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.
Hydroxyl group termination for nucleation of a dielectric metallic oxide
A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.
SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES
Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A semiconductor device includes a substrate, a gate structure over the substrate, and source/drain regions in the substrate and on opposite sides of the gate structure. The gate structure includes an interfacial layer, a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and a gate electrode over the QAFE layer. The QAFE layer includes Hf.sub.1−xZr.sub.xO.sub.2, in which x is greater than 0.5 and is lower than 1.
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS
A substrate processing method includes a fluorine-based gas supply step of supplying a fluorine-based gas into a processing chamber where a substrate having a silicon-based film is accommodated, a purge gas supply step of supplying a purge gas for discharging the supplied fluorine-based gas into the processing chamber. The substrate processing method further includes a nitrogen-based gas supply step of supplying a nitrogen-based gas into the processing chamber from which the fluorine-based gas has been discharged. In the substrate processing method, at least in the fluorine-based gas supply step and the purge gas supply step, a temperature of the substrate is maintained at 60° C. or less.
High-K Dielectric and Method of Manufacture
A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO.sub.2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (Hf.sub.xTi.sub.1-xO.sub.2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.