Patent classifications
H01L21/28194
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC EQUIPMENT
There is provided a semiconductor device including a channel portion, and a gate electrode provided on a side opposite to the channel portion with a gate insulating film interposed between the gate electrode and the channel portion, in which the gate insulating film incudes a first portion having a first transition metal oxide, and a second portion having a second transition metal oxide and cation species and having a concentration of the cation species different from the first portion.
SURFACE FUNCTIONALIZATION AND PASSIVATION WITH A CONTROL LAYER
Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiN.sub.x monolayer at temperatures below about 300° C.
Methods of forming a semiconductor device by thermally treating a cleaned surface of a semiconductor substrate in a non-oxidizing ambient
The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.
RARE-EARTH MATERIALS FOR INTEGRATED CIRCUIT STRUCTURES
Disclosed herein are rare-earth materials, structures, and methods for integrated circuit (IC) structures. For example, in some embodiments, a precursor for atomic layer deposition (ALD) of a rare-earth material in an IC structure may include a rare-earth element and a pincer ligand bonded to the rare-earth element.
Semiconductor device and semiconductor device manufacturing method
A semiconductor device according to the present invention includes a semiconductor layer, a gate trench defined in the semiconductor layer, a first insulating film arranged on the inner surface of the gate trench, a gate electrode arranged in the gate trench via the first insulating film, and a source layer, a body layer, and a drain layer arranged laterally to the gate trench, in which the first insulating film includes, at least at the bottom of the gate trench, a first portion and a second portion with a film elaborateness lower than that of the first portion from the inner surface of the gate trench in the film thickness direction.
Film structure including hafnium oxide, electronic device including the same, and method of manufacturing the same
Provided are a film structure including hafnium oxide, an electronic device including the same, and a method of manufacturing the same. The film structure including hafnium oxide includes a hafnium oxide layer including hafnium oxide crystallized in a tetragonal phase, and first and second stressor layers apart from each other with the hafnium oxide layer therebetween and applying compressive stress to the hafnium oxide layer.
Semiconductor ferroelectric storage transistor and method for manufacturing same
Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
Fringe capacitance reduction for replacement gate CMOS
A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.
Method of Forming a Dielectric Through Electrodeposition on an Electrode For a Capacitor
The present invention relates to a method for forming a capacitor having carbon or metal electrodes and an electrolyte which is also a source of electropolymerisable anions. Applying a sufficiently positive voltage, a thin dielectric layer forms at the positive electrode, enabling the use of cell voltages higher than 3.5 V. The construction and characteristics of capacitors with 5, 6.3, and 10 V of cell voltages, having reduced graphene oxide electrodes and an ionic liquid electrolyte, are shown. Further, a method of forming a capacitor, including the steps of: (a) providing a first electrode; (b) providing a first electrolyte including an anionic compound, wherein said compound includes at least one cyano group or at least one nitrile group; (c) electropolymerising said anionic compound in order to form a dielectric layer on at least part of the first electrode; (d) forming a capacitor including the electrode of step (c), a second electrode and a second electrolyte, which is the same or different to the first electrolyte, is claimed. In a further aspect of the invention, there is provided an electronic device including a capacitor, a transistor or an electrode produced by means of a method as defined above. It is believed that a number of dielectric compounds produced by the method as defined above are new compounds not previously isolated. Accordingly, polytetracyanoborate, polycyani, or polytricyanomethanide.
FLUORINATION DURING ALD HIGH-K, FLUORINATION POST HIGH-K AND USE OF A POST FLUORINATION ANNEAL TO ENGINEER FLUORINE BONDING AND INCORPORATION
Embodiments of the present disclosure generally relate to methods for forming a high-k gate dielectric in a transistor. The high-k gate dielectric may be formed by introducing a fluorine containing gas into a processing chamber during the deposition of the high-k gate dielectric in the processing chamber. In one embodiment, the high-k gate dielectric is formed by an ALD process in a processing chamber, and a fluorine containing gas is introduced into the processing chamber during one or more stages of the ALD process. Fluorine ions, molecules or radicals from the fluorine containing gas (may be activated by a plasma) can fill the oxygen vacancies in the high-k dielectric.