A negative capacitance semiconductor device includes a substrate. A dielectric layer is disposed over a portion of the substrate. A ferroelectric structure is disposed over the dielectric layer. Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure. A gate electrode is disposed over the ferroelectric structure.

Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-K dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC).

Methods and systems for depositing threshold voltage shifting layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a threshold voltage shifting layer onto a surface of the substrate.

A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

A semiconductor structure includes a semiconductor substrate, with first, second, and third field effect transistors (FETs) formed on the substrate. A gate of the first FET includes a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK); a gate of the second FET includes the first WFM layered with a second IL, a second HK, and a first dipole material; and a gate of the third FET includes the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material. The first FET does not include the first dipole material and does not include the second dipole material, and the second FET does not include the second dipole material.

Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source. In some embodiments, related semiconductor device structures may include a doped metal oxide film formed by cyclical deposition processes.

A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.