Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; performing a first treatment by introducing a trap-repairing element on the first and second dielectric layers; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; and forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions.

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.

A method for preparing a semiconductor structure includes: providing a substrate which includes a device region and a shallow trench isolation region surrounding the device region, in which the device region is exposed from a surface of the substrate; depositing a barrier layer on the substrate, the barrier layer at least covering the device region; forming an initial oxide which is located in the device region and in contact with the barrier layer; and removing part of the initial oxide to form a device oxide.

Embodiments of the present disclosure generally relate to inductively coupled plasma sources, plasma processing apparatus, and independent temperature control of plasma processing. In at least one embodiment, a method includes introducing a process gas into a gas injection channel and generating an inductively coupled plasma within the gas injection channel. The plasma includes at least one radical species selected from oxygen, nitrogen, hydrogen, NH and helium. The method includes delivering the plasma from the plasma source to a process chamber coupled therewith by flowing the plasma through a separation grid between the plasma source and a substrate. The method includes processing the substrate. Processing the substrate includes contacting the plasma including the at least one radical species with a first side of the substrate facing the separation grid and heating the substrate using a plurality of lamps located on a second side of the substrate opposite the separation grid.

Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

The present application relates to the technical field of semiconductors, and provides a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate with trench structures; forming a source region and a drain region respectively on both sides of each of the trench structures; forming an oxide layer, the oxide layer including a first oxide portion covering side walls of each of the trench structured and a second oxide portion covering a bottom wall of each of the trench structures, and a thickness of the second oxide portion being less than a thickness of the first oxide portion; and nitriding the oxide layer, so that a concentration of nitrogen ions in the first oxide portion is less than a concentration of nitrogen ions in the second oxide portion.

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).