A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon; a third electrode provided above the second electrode, the third electrode facing the first semiconductor region and the second semiconductor region via a second insulating film containing silicon oxide; a third insulating film provided between the second electrode and the third electrode, the third insulating film containing silicon nitride; a third semiconductor region of first conductivity type provided on the first semiconductor region; a fourth semiconductor region of first conductivity type provided on the second semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided on the interlayer insulating film, the fourth electrode being electrically connected to the third semiconductor region and the fourth semiconductor region.

In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-κ dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer.

A semiconductor device includes a source region, a drain region, a SiGe channel region, an interfacial layer, a high-k dielectric layer and a gate electrode. The source region and the drain region are over a substrate. The SiGe channel region is laterally between the source region and the drain region. The interfacial layer forms a nitrogen-containing interface with the SiGe channel region. The high-k dielectric layer is over the interfacial layer. The gate electrode is over the high-k dielectric layer.

A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

The present disclosure relates to a manufacturing method of LTPS TFT substrate and the LTPS TFT substrate. With respect to the manufacturing method, after the gate insulation layer is formed, the gate insulation layer is doped with nitrogen by a plasma containing nitrogen so as to increase the positive charges within the gate insulation layer. As such, the P-type TFT threshold voltage can be negatively shifted so as to enhance the splash screen issue.

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

A method and a device for forming a highly dielectric metal oxide layer. The method includes repeatedly causing a plasma-off period and a plasma-on period while an organic metal compound and an oxidizing agent are continuously injected into a chamber. One cycle includes one plasma-off period and one plasma-on period. During the plasma-off period, a physical and chemical adsorption layer including an organic metal compound and a plurality of atomic layers is formed on a substrate. During the plasma-on period, a metal oxide layer that is thicker than two atomic layers is formed by a chemical reaction of metal atoms in the physical and chemical adsorption layer and oxygen atoms in the oxidizing agent.

A PNA temperature monitoring method comprises: Step 1, forming zero mark layer patterns on a tested silicon substrate; Step 2, forming a nitrogen-doped gate oxide by the following process: growing an oxide layer, doping the oxide layer with nitrogen, and carrying out PNA; Step 3, forming overlay layer patterns, and overlaying the overlay layer patterns and the corresponding zero mark layer patterns to form monitoring structures; and Step 4, measuring overlay values of the overlay layer patterns and the corresponding zero mark layer patterns of the monitoring structures, and regulating a PNA temperature according to the measured overlay values. By adoption of the method, the influence of the PNA temperature on a gate oxide in a two-dimensional plane can be monitored, and then the PNA temperature can be regulated to increase product yield.