Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A method for improving a bias temperature instability of a SiO.sub.2 layer comprises exposing the SiO.sub.2 layer to atomic hydrogen.

A method for making an LDMOS device including forming a first ion doped region in an epitaxial layer of a first region and removing a first oxide layer of the first region, the first oxide layer being formed on the epitaxial layer; forming a second oxide layer on the epitaxial layer and the remaining first oxide layer; forming a second ion doped region in the epitaxial layer of a second region, the first region and the second region having no overlapped region; and forming a polysilicon layer on the second oxide layer; removing the polysilicon layer, the first oxide layer and the second oxide layer of a third region.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.

A method for forming an oxide layer includes forming an interfacial layer on a substrate, forming an amorphous silicon layer on the interfacial layer, performing a direct oxidation process to selectively oxidize the formed amorphous silicon layer, and performing a thermal oxidation process to oxidize the formed amorphous silicon layer.

Described examples include a method having steps of forming an isolation pad oxide layer on a substrate and forming and patterning a silicon nitride layer on the isolation pad oxide layer. The method also has steps of oxidizing portions of the substrate not covered by the silicon nitride layer to form a LOCOS layer and oxidizing the silicon nitride layer in an oxidizing ambient containing a chlorine source to form a silicon dioxide layer.

A semiconductor device includes: a substrate having a groove formed on a main surface; a drift region of a first conductivity type, the drift region having a portion disposed at a bottom part; a well region of a second conductivity type, the well region being disposed in one sidewall to be connected to the drift region; a first semiconductor region of the first conductivity type, the first semiconductor region being disposed on a surface of the well region in the sidewall to be away from the drift region; a second semiconductor region of the first conductivity type, the second semiconductor region being disposed to be opposed to the well region via the drift region; and a gate electrode opposed to the well region, the gate electrode being disposed in a gate trench that has an opening extending over the upper surfaces of the well region and the first semiconductor region.

A method for manufacturing a semiconductor structure includes: providing a substrate; forming at least a pair of first side walls on the substrate, an interval being provided distance between two first side walls in each pair; forming a second side wall at either side of each of the first side walls by an In-Situ Steam Generation (ISSG) process, and forming a gate oxide layer on the substrate between the two first side walls in each pair; and forming a gate layer on a surface of the gate oxide layer.