A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.

A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

The present disclosure a method for manufacturing a metal-oxide-semiconductor (MOS) transistor device. The method includes steps of providing a substrate; forming a gate electrode over the substrate; forming a source region and a drain region in the substrate; depositing an isolating layer over the substrate and the gate electrode; forming a plurality of contact holes in the isolating layer to expose the gate electrode, the source region, and the drain region; forming a plurality of metal contacts in the gate electrode, the source region, and the drain region; depositing a contact liner in the contact holes; and depositing a conductive material in the contact holes, wherein the conductive material is surrounded by the contact liner.

A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.

Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×10.sup.21 atoms per cubic centimeter (at./cm.sup.3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

There is provided a technique that includes selectively doping a metal film with a dopant by performing: supplying a dopant-containing gas containing the dopant to a substrate in which the metal film and a film other than the metal film are formed on a film in which the dopant is doped; and removing the dopant-containing gas from above the substrate.