This invention provides a manufacture method for an interconnection structure including the following steps: forming a first dielectric layer over a first conductive terminal; forming a conductor pillar penetrating through the first dielectric layer, wherein the conductor pillar is electrically connected to the first conductive terminal but not electrically connected to a first conduction layer over the first dielectric layer; forming an upper dielectric layer over the first conduction layer; and forming an upper conduction layer over the upper dielectric layer, wherein the conductor pillar is connected to the upper conduction layer.

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.

A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

A memory device includes: first and second bit lines on a dielectric layer; first and second word lines between the first and second bit lines; a source line between the first and second word lines; a channel pillar penetrating through the first word line, the source line and the second word line, and connected to the first bit line, the source line, and the second bit line; a first charge storage structure surrounding a top surface and a bottom surface of the first word line and between a sidewall of the first word line and a lower portion of a sidewall of the channel pillar; and a second charge storage structure, surrounding a top surface and a bottom surface of the second word line and between a sidewall of the second word line and an upper portion of the sidewall of the channel pillar.

An apparatus comprising a memory array comprising wordlines, digit lines, and memory cells, with each memory cell coupled to an associated wordline and an associated digit line. Each memory cell comprises a monocrystalline silicon material adjacent to an access device, a monocrystalline metal silicide material directly contacting the monocrystalline semiconductor material, a metal material directly contacting the monocrystalline metal silicide material, and a storage device adjacent to the metal material. Electronic devices, electronic systems, and methods of forming an electronic device are also disclosed.

The embodiments provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a substrate including an active region and a shallow trench isolation region spaced apart from each other; a plurality of isolation structures arranged on a surface of the substrate; a plurality of grooves arranged between the plurality of isolation structures, wherein a bottom of the groove has a first inclined plane, and the first inclined plane is formed in the active region; and a conductive plug arranged in the groove. According to embodiments of the present disclosure, it is avoidable that an air gap is formed inside a polycrystalline silicon in the fabrication process of a storage node contact (SNC) structure.