Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.

A semiconductor device includes a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode having a metal layer, a metal oxide layer and a silicon layer containing a dopant, provided sequentially on the gate insulating film; and a transistor having a gate insulating film and a gate electrode.

Provided are nanocrystalline graphene and a method of forming the nanocrystalline graphene through a plasma enhanced chemical vapor deposition process. The nanocrystalline graphene may have a ratio of carbon having an sp.sup.2 bonding structure to total carbon within the range of about 50% to 99%. In addition, the nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm.

The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.

Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.

Each imaging pixel provided in a solid-state imaging device includes a charge accumulation part which is a diffusion region formed in a substrate, a gate electrode formed lateral to the charge accumulation part on the substrate, an insulating film formed on the charge accumulation part, and a contact plug connected to the charge accumulation part so as to penetrate the insulating film and made of semiconductor. The contact plug is, at a lower part thereof, embedded in the insulating film, and is, at an upper part thereof, exposed through the insulating film. Silicide is formed on the upper part of the contact plug, and the charge accumulation part and the gate electrode are covered by the insulating film.