A Schottky diode may include a substrate; an epitaxial layer deposited on top of the substrate; one or more trenches formed on top of the epitaxial layer; an implantation region at a bottom portion of each trench; an ohmic contact metal on the other side of the substrate; a first Schottky contact metal deposited onto the implantation region in each trench to form a first Schottky junction between the first Schottky contact metal and the epitaxial layer at a lower trench sidewall; a second Schottky contact metal filling each trench and extending a predetermined length to each corner of mesas on the epitaxial layer to form a second Schottky junction between the second Schottky contact metal and the epitaxial layer at an upper trench sidewall; and a third Schottky contact metal covering the second Schottky contact metal and the epitaxial layer to form a third Schottky junction.

A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.

A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a Schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The Schottky-junction forming material forms at least one Schottky contact with the amorphous n-doped semiconductor surface layer.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

In the present invention, a contact layer formed of a material having an electron concentration of less than 110.sup.22 cm.sup.3 is directly provided on a surface of a semiconductor crystal having an n-type conductivity with a band gap of 1.2 eV or less at room temperature. Consequently, the wave function penetration from the contact layer side to the semiconductor surface side is reduced. As a result, the formation of the energy barrier height.Math..sub.B due to the Fermi level pinning phenomenon is much suppressed. It is possible to achieve the contact with a lower resistivity and with high ohmic properties.

A trench power transistor includes a semiconductor body having opposite first and second surfaces, and including at least one active region. Such region includes a trench electrode structure, a well, and a source. The trench electrode structure has an electrode trench recessed from the first surface, and includes first, second, and third insulating layers sequentially disposed over bottom and surrounding walls of the electrode trench, a shield electrode enclosed by the third insulating layer, a fourth insulating layer disposed on the first, second, and third insulating layers, and a gate electrode surrounded by the fourth insulating layer. The second insulating layer made of a nitride material and the fourth insulating layer are different in material. A production method of the transistor is also disclosed.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.