A method of fabricating semiconductor device is provided. The method includes providing a substrate having a trench, plasma-ionizing a gas which comprises a deposition material precursor and a doping material precursor to respectively obtain a plasma-ionized deposition material and a plasma-ionized doping material, and depositing the plasma-ionized deposition material and the plasma-ionized doping material in the trench by applying a bias voltage to a bottom surface of the trench, wherein the bottom surface of the trench comprises a first material, and sidewalls of the trench comprise a second material different from the first material.

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.

A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.

Provided herein are methods of forming conductive cobalt (Co) interconnects and Co features. The methods involve deposition of a thin manganese (Mn)-containing film on a dielectric followed by subsequent deposition of cobalt on the Mn-containing film. The Mn-containing film may be deposited on a silicon-containing dielectric, such as silicon dioxide, and annealed to form a manganese silicate.

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.

Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.

A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

In one embodiment, the present disclosure may be directed to a method for impedance matching. A matching network is positioned between a radio frequency (RF) source and a plasma chamber. The RF source is configured to provide at least two non-zero pulse levels, and the matching network includes at least one electronically variable capacitor (EVC) configured to alter its capacitance to provide a match configuration. For each of the pulse levels, at a regular time interval, the method determines a first parameter value for a first parameter related to the plasma chamber or matching network. For each of the pulse levels, the method carries out a separate matching process based on the determined parameter values for the pulse level.

A semiconductor device comprising a manifold for uniform vapor deposition is disclosed. The semiconductor device can include a manifold comprising a bore and having an inner wall. The inner wall can at least partially define the bore. A first axial portion of the bore can extend along a longitudinal axis of the manifold. A supply channel can provide fluid communication between a gas source and the bore. The supply channel can comprise a slit defining an at least partially annular gap through the inner wall of the manifold to deliver a gas from the gas source to the bore. The at least partially annular gap can be revolved about the longitudinal axis.