The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8.

A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.

A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.

A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.

The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.

Methods and apparatuses for controlling precursor flow in a semiconductor processing tool are disclosed. A method may include flowing gas through a gas line, opening an ampoule valve(s), before a dose step, to start a flow of precursor from the ampoule to a process chamber through the gas line, closing the ampoule valve(s) to stop the precursor from flowing out of the ampoule, opening a process chamber valve, at the beginning of the dose step, to allow the flow of precursor to enter the process chamber, and closing the process chamber valve, at the end of the dose step, to stop the flow of precursor from entering the process chamber. A controller may include at least one memory and at least one processor and the at least one memory may store instructions for controlling the at least one processor to control precursor flow in a semiconductor processing tool.

A method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapor deposition in a reactor, includes adjusting a deposition temperature between 605° C.-800° C. in a process chamber of the reactor, and depositing the one or more polycrystalline silicon layers on the substrate by using a silicon source gas including SiH4 or SiH2Cl2, and a dopant gas including BCl3.

A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first surface area state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first surface area state to a second surface area state having a second surface area different from the first surface area. The method still further includes forming the film by changing the flow rate of the reaction gas from the first flow rate to a second flow rate different from the first flow rate after detecting the transition from the first surface area state to the second surface area state.

Chemical vapor deposition (CVD) processes which use a ruthenium precursor of formula R.sup.1R.sup.2Ru(0), wherein R.sup.1 is an aryl group-containing ligand, and R.sup.2 is a diene group-containing ligand and a reducing gas a described. The CVD can include oxygen after an initial deposition period using the ruthenium precursor and reducing gas. The method can provide selective Ru deposition on conductive materials while minimizing deposition on non-conductive or less conductive materials. Further, the subsequent use of oxygen can significantly improve deposition rate while minimizing or eliminating oxidative damage of the substrate material. The method can be used to form Ru-containing layers on integrated circuits and other microelectronic devices.