An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

The present disclosure relates to a substrate processing method and apparatus which can supply gas to a plurality of process chamber through one gas supply unit, and supply different gases at the same time, thereby improving the uniformity of the thicknesses of thin films deposited in the respective chambers.

The substrate processing method and apparatus can perform a process in only one chamber by supplying gas to only the chamber at the same time or perform different processes in the plurality of chambers by supplying different gases to the respective chambers. Therefore, films having uniform thicknesses can be deposited in the respective chambers, and the gas supply efficiency can be improved.

Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.

A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

The present disclosure relates to a semiconductor device and a method for forming a semiconductor device with a graphene conductive structure. The semiconductor device includes a first gate structure disposed over a semiconductor substrate, and a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure. The semiconductor device also includes a first silicide layer disposed in the semiconductor substrate and over the first source/drain region, and a graphene conductive structure disposed over the first silicide layer. The semiconductor device further includes a first dielectric layer covering the first gate structure, and a second dielectric layer disposed over the first dielectric layer. The graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer.

Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

A method of depositing a material film on a substrate within a reaction chamber by a cyclical deposition process is disclosed. The method may include: contacting the substrate with a first vapor phase reactant and purging the reaction chamber with a first main purge. The method also includes: contacting the substrate with a second vapor phase reactant by two or more micro pulsing processes, wherein each micro pulsing process comprises: contacting the substrate with a micro pulse of a second vapor phase reactant; and purging the reaction chamber with a micro purge, wherein each of the micro pulses of the second vapor phase reactant provides a substantially constant concentration of the second vapor phase reactant into the reaction chamber. The method may also include; purging the reaction chamber with a second main purge. Device structures including a material film deposited by the methods of the disclosure are also disclosed.

A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×10.sup.22 cm.sup.−3 or more, a SiO.sub.2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO.sub.2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO.sub.2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO.sub.2 layer and that has a carbon density of 1.0×10.sup.19 cm.sup.−3 or less.

There is provided a gas processing apparatus, including: a vacuum vessel; a mounting part installed in the vacuum vessel and configured to mount a substrate; an opposing part configured to face the mounting part and including first gas discharge ports configured to discharge a processing gas to the substrate; a first diffusion space configured to communicate with the first gas discharge ports; second gas discharge ports formed in a ceiling portion and configured to supply the processing gas to a central portion of the first diffusion space; a second diffusion space configured to communicate with the second gas discharge ports; a gas supply path installed at an upstream side of the second diffusion space and configured to supply the processing gas to the second diffusion space; and third gas discharge ports configured to be opened to an outer portion of the ceiling portion in an oblique direction.