The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.

A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.

Molybdenum (Mo) metal-on-metal (MoM) deposition methods for providing true bottom-up fill in vias and/or other gap features in device structures. These device structures contain metal at the bottom surface and have dielectric sidewalls. The deposition process provides molybdenum growth only, in some cases, on the metal film/layer to provide a selective process that can be called a metal-on-metal (MoM) process. The Mo MoM deposition process described herein are not limited to thin films (e.g., films less than 50 Å) and can be used to deposit thicker films (e.g., greater than 50 Å in some cases and greater than 200 Å in other useful cases) on metal surfaces while no, or substantially no, deposition is found on dielectric surfaces.

Molybdenum (Mo) metal-on-metal (MoM) deposition methods for providing true bottom-up fill in vias and/or other gap features in device structures. These device structures contain metal at the bottom surface and have dielectric sidewalls. The deposition process provides molybdenum growth only, in some cases, on the metal film/layer to provide a selective process that can be called a metal-on-metal (MoM) process. The Mo MoM deposition process described herein are not limited to thin films (e.g., films less than 50 Å) and can be used to deposit thicker films (e.g., greater than 50 Å in some cases and greater than 200 Å in other useful cases) on metal surfaces while no, or substantially no, deposition is found on dielectric surfaces.

Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

A niobium compound and a method of forming a thin film using the niobium compound, the compound being represented by the following General formula I: ##STR00001## wherein, in General formula I, R.sup.1, R.sup.4, R.sup.5, R.sup.6, R.sup.7, and R.sup.8 are each independently a hydrogen atom, a C1-C6 linear or branched alkyl group or a C3-C6 cyclic hydrocarbon group, at least one of R.sup.4, R.sup.5, R.sup.6, R.sup.7, and R.sup.8 being a C1-C6 linear or branched alkyl group, and R.sup.2 and R.sup.3 are each independently a hydrogen atom, a halogen atom, a C1-C6 linear or branched alkyl group, or a C3-C6 cyclic hydrocarbon group.

A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.