A methodology for (a) the etching of films of Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, W, Mo, Co, Ru, SiN, or TiN, or (b) the deposition of tungsten onto the surface of a film chosen from Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, W, Mo, Co, Ru, Ir, SiN, TiN, TaN, WN, and SiO.sub.2, or (c) the selective deposition of tungsten onto metallic substrates, such as W, Mo, Co, Ru, Ir and Cu, but not metal nitrides or dielectric oxide films, which comprises exposing said films to WOCl.sub.4 in the presence of a reducing gas under process conditions.

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Some embodiments of the disclosure relate to methods for forming a bottom-up tungsten gapfill. Some embodiments of the disclosure relate to methods for reducing the deposition rate of tungsten by chemical vapor deposition. A molybdenum halide precursor is added to a tungsten halide precursor and a reductant. The co-flow of tungsten halide and molybdenum halide demonstrates either reduced or eliminated tungsten growth.

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μm.sup.2 or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Semiconductor device is provided. The semiconductor device includes a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region. A first work function layer is formed on the base substrate in the second region. A second work function layer is formed on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features.