A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.

A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.

Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

There is provided a technique that includes: (a) supplying a molybdenumcontaining gas containing molybdenum and oxygen to a substrate in a process chamber; (b) supplying an additive gas containing hydrogen to the substrate; and (c) supplying a reducing gas containing hydrogen and having a chemical composition different from that of the additive gas to the substrate, wherein at least two of (a), (b), and (c) are performed simultaneously or to partially overlap with each other in time one or more times or (a), (b), and (c) are performed sequentially one or more times to form a molybdenum film on the substrate.

A reaction chamber includes a chamber body and a base. The base is arranged in the chamber body. The base includes a carrier member, a first block ring, and a second block ring. The carrier member is configured to carry a substrate and an edge member arranged around the carrier member. A height of an upper surface of the carrier member is greater than a height of an upper surface of the edge member. The first block ring is arranged on the upper surface of the edge member and around the carrier member. The upper surface of the carrier member is higher than an upper surface of the first block ring. The second block ring is on the upper surface of the first block ring. The second block ring includes a body member and a shield member.

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

A semiconductor device manufacturing method comprising loading a substrate into a substrate treatment apparatus, performing a deposition process on the substrate, and cleaning the substrate treatment apparatus. The substrate treatment apparatus includes a housing defining a treatment area in which the deposition process is performed, a gas supply supplying a first process gas at a flow rate of 1000 sccm to 15000 sccm and supplying a second process gas, a remote plasma supply connected to the gas supply, generating a first process plasma and a second process plasma by applying RF power to plasma-process the first process gas and the second process gas, and a shower head installed in the housing to supply the first process plasma and the second process plasma to the treatment area. The second process plasma cleans a membrane material deposited on an inner wall of the housing.

A semiconductor manufacturing method using a semiconductor manufacturing apparatus 100 including a treating chamber 1, the method including: a first process of supplying a complexing gas into the treating chamber in which a wafer 2 having a surface having a transition metal-containing film formed thereon is placed, to adsorb an organic compound as a component of the complexing gas to the transition metal-containing film, the transition metal-containing film containing a transition metal element; and a second process of heating the wafer in which the organic compound is adsorbed to the transition metal-containing film, to react the organic compound with the transition metal element, thereby converting the organic compound into an organometallic complex, and desorbing the organometallic complex, wherein the organic compound has Lewis basicity, and is a multidentate ligand molecule capable of forming a bidentate or more coordination bond with the transition metal element.