A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer, and forming a tri-layer gate having a gate foot in the first opening, a gate neck extending from the gate foot, and a gate head extending from the gate neck. The gate foot has a first width, and the gate neck has a second width that is wider than the first width. The gate neck extends for a length over the dielectric passivation layer on both sides of the first opening. The gate head has a third width wider than the second width of the gate neck.

A semiconductor device includes a channel layer including a channel; a channel supply layer on the channel layer; a channel separation pattern on the channel supply layer; a gate electrode pattern on the channel separation pattern; and an electric-field relaxation pattern protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.

A semiconductor device includes a barrier layer, a dielectric layer, a first spacer, a second spacer, and a gate. The dielectric layer is disposed on the barrier layer and defines a first recess. The first spacer is disposed on the barrier layer and within the first recess. The second spacer is disposed on the barrier layer and within the first recess. The first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer. The top surface of the portion of the barrier layer is recessed. The gate is disposed on the barrier layer, the dielectric layer, and the first and second spacers, in which the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.

A semiconductor device includes a barrier layer, a dielectric layer, a first protection layer, a first spacer, and a gate. The dielectric layer is disposed on the barrier layer. The first protection layer is disposed on the barrier layer, in which the first protection layer extends from a first sidewall of the dielectric layer to a top surface of the barrier layer. The first spacer is disposed on and received by the first protection layer, in which a top end of the first protection layer comprises a first curved surface between the first spacer and the dielectric layer. The gate is disposed on the barrier layer, the dielectric layer, and the first spacer. The gate extends from a top surface of the dielectric layer and at least along the first curved surface of the first protection layer to make contact with the top surface of the barrier layer.

This invention concerns a gate structure and a process for its manufacturing. In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thermo-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal). The gate structure according to the invention comprises a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, the intermediate layer-having a recess extending through the entire intermediate layer towards the active layer; and a contact element which is arranged within the recess, the contact element completely filling the recess and extending to above the intermediate layer, the contact element resting at least in sections directly on the intermediate layer; the contact element being made of a Schottky metal and the contact element having an interior cavity completely enclosed by the Schottky metal.

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

A microwave transistor has a patterned region between a source and a drain on a barrier layer. Within the patterned region, the surface of the barrier layer partially recessed downwards in the thickness direction to form a plurality of grooves. A gate covers the patterned region. The length of the gate is greater than the lengths of the grooves in the length direction of the gate, so as to completely cover the grooves. In one aspect, by arranging the grooves, the gate control capability of a component is improved and the short-channel effect is suppressed; in another aspect, an original heterostructure below the gate is preserved; in this way, the reduction of the conductive capability due to the reduction of the two-dimensional electron gas density is avoided; and accordingly the current output capability of the component is ensured while the short-channel effect is suppressed.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a barrier layer disposed above the substrate, and a dielectric layer disposed on the barrier layer and defining a first recess. The semiconductor device further includes a spacer disposed within the first recess and a gate disposed between a first portion of the spacer and a second portion of the spacer, wherein the gate defining a first recess.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer. The semiconductor device further includes a dielectric layer disposed on the barrier layer and defining a first recess exposing a portion of the barrier layer. The semiconductor device further includes a first spacer disposed within the first recess, wherein the first spacer comprises a surface laterally connecting the dielectric layer to the barrier layer.

A method of manufacturing a semiconductor device including a substrate; a first nitride layer containing gallium on the substrate; and a second nitride layer containing silicon on the first nitride layer includes generating an etchant of a gas containing chlorine atoms or bromine atoms; and selectively removing the second nitride layer, wherein the etchant is generated by plasma discharge of the gas, wherein the second nitride layer and the first nitride layer are prevented from being irradiated with ultraviolet rays generated at a time of the plasma discharge, and wherein the selectively removing the second nitride layer includes etching the second nitride layer under a first atmosphere at a first pressure that is lower than a first saturated vapor pressure of a silicon compound and that is higher than a second saturated vapor pressure of a gallium compound.