Patent classifications
H
ELECTRICITY
Load children
H01
ELECTRIC ELEMENTS
Load children
H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
Load children
2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/10
Bump connectors; Manufacturing methods related thereto
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/12
Structure, shape, material or disposition of the bump connectors prior to the connecting process
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13
of an individual bump connector
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13001
Core members of the bump connector
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/131
with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13163
the principal constituent melting at a temperature of greater than 1550°C
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/13178
Iridium [Ir] as principal constituent
Filter patents View analytics View as hierarchy Open in page

H01L2224/13178

Solder based hybrid bonding for fine pitch and thin BLT interconnection
12394740 · 2025-08-19 · ·

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

SOLDER BASED HYBRID BONDING FOR FINE PITCH AND THIN BLT INTERCONNECTION
20250372559 · 2025-12-04 ·

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.