Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

A bonded assembly including: a first electronic component including a first substrate and a plurality of first electrodes disposed in a pressed area at a first height from a surface of the first substrate; a second electronic component including a second substrate and a plurality of second electrodes disposed at a second height from a surface of the second substrate, a second electrode overlapping with a corresponding first electrode to face the first electrode; a conductive bonding layer disposed between the first electrode and the second electrode overlapped with each other to bond the first electrode and the second electrode; and at least one spacer disposed between the first substrate and the second substrate to overlap the pressed area, the at least one spacer having a thickness that is greater than a value obtained by summing the first height and the second height.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a recess filled with a conductive material electrically coupled to at least one of the plurality of conductive traces. The semiconductor structure also includes semiconductor chip. The semiconductor chip includes a plurality of conductive pads correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.

Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

A chip package includes a chip, an isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the isolation layer, and is in electrical contact with the conductive pad. The passivation layer is located on the isolation layer and the redistribution layer. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, and has a flat surface facing away from the chip.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

A semiconductor package includes a first semiconductor chip positioned above a first substrate. A second substrate is positioned above the first substrate. The first semiconductor chip is positioned between the first substrate and the second substrate. A plurality of support structures are disposed between the second substrate and the first semiconductor chip. Connection members are disposed between the first substrate and the second substrate. The connection members electrically connect the first substrate to the second substrate. A molding layer fills a space between the first substrate and the second substrate. The molding layer is disposed on the first semiconductor chip and the connection members.

According to one embodiment, a semiconductor device includes a semiconductor substrate and an array portion. The array portion includes a plurality of metal portions arranged on the semiconductor substrate. When a virtual quadrilateral circumscribing minimally a contour shape of the array portion on the semiconductor substrate is set, the contour shape of the array portion does not overlap each of four vertices of the virtual quadrilateral.

A semiconductor package includes a first semiconductor chip including a first surface and a second surface opposite to the first surface, a second semiconductor chip stacked on the first surface of the first semiconductor chip, and a molding layer contacting the first surface of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer includes a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip, a second sidewall from the first height to a second height in the first direction, and a flat surface that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.