H01L2224/29166

Method for replacing or patching element of display device
11784099 · 2023-10-10 · ·

A method for replacing an element of a display device includes: forming a structure with a first liquid layer between a first micro device and a conductive pad of a substrate in which the first micro device is gripped by a sticking force produced by the first liquid layer; evaporating the first liquid layer such that the first micro device is bound to the substrate; determining if the first micro device is malfunctioned or misplaced; removing the first micro device when the first micro device is malfunctioned or misplaced; forming another structure with a second liquid layer between a second micro device and the conductive pad of the substrate in which the second micro device is gripped by a sticking force produced by the second liquid layer; and evaporating the second liquid layer such that the second micro device is bound to the substrate.

SEMICONDUCTOR DEVICE
20230282535 · 2023-09-07 ·

A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.

SEMICONDUCTOR DEVICE
20230282535 · 2023-09-07 ·

A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.

STEPPED MICRO-LENS ON MICRO-LED

A light source includes a backplane including electrical circuits fabricated thereon, an array of micro-light emitting diodes (micro-LEDs) bonded to the backplane and configured to emit visible light, and an array of micro-lenses aligned with the array of micro-LEDs and configured to collimate the visible light emitted by the array of micro-LEDs. Each micro-lens of the array of micro-lenses has a plurality of discrete thickness levels. A pitch of the array of micro-lenses is equal to or less than about 5 μm, such as about 2 μm. The pitch of the array of micro-lenses can be the same as or different from the pitch of the array of micro-LEDs.

BGA STIM package architecture for high performance systems

Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

BGA STIM package architecture for high performance systems

Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

LIQUID PHASE BONDING FOR ELECTRICAL INTERCONNECTS IN SEMICONDUCTOR PACKAGES

Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.

DISPLAY MODULE INCLUDING MICRO LIGHT EMITTING DIODES

Provided is a display assembly including a plurality of light emitting diodes, a plurality of electrodes provided on the plurality of light emitting diodes, a substrate, a plurality of electrode pads provided on the substrate, the plurality of electrode pads being connected to the electrodes provided on the plurality of light emitting diodes, and an adhesive layer fixing the plurality of light emitting diodes to the substrate, wherein the adhesive layer includes a non-conductive polymer resin, a flux agent mixed with the non-conductive polymer resin, and a plurality of conductive particles dispersed in the non-conductive polymer resin and connecting the electrodes of the light emitting diodes and the plurality of electrode pads.

Integrated fan-out packaging

The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Method for Fastening a Semiconductor Chip on a Substrate, and Electronic Component
20220208715 · 2022-06-30 ·

In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate, wherein the solder metal layer sequence includes a first metallic layer including an indium-tin alloy, a barrier layer arranged above the first metallic layer, and a second metallic layer having gold arranged between the barrier layer and the semiconductor chip, and wherein the indium-tin alloy has the following formula: In.sub.xSn.sub.1-x with 0.04≤x≤0.2.