A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.

A transmitter (TX)-side feedforward equalizer (FFE) includes one or more “roaming” filter taps which can be used to compensate reflections that occur at unpredictable and substantial time offsets from a main pulse. The roaming filter taps are realized in a hardware- and power-efficient manner by implementing a programmable delay serializer in which the phases of multi-rate clocks are switched to introduce binary weighted delays on the roaming tap. In this way a variable difference in latencies is introduced between the main and the roaming tap data paths. The TX-side FFE implementations provide a fully programmable roaming tap generator having a 1-Unit Interval (UI) resolution of delay setting integrated into the data serializer of the TX macro.

A method and apparatus for signal equalization are provided. Multiple decision components are arranged in a sequence, beginning with a history portion and ending with a decode portion. Each decision component performs a decode decision on a symbol. Decode decisions are passed forward to other decision components where they can be used to compensate for intersymbol interference. Decode decision output by the history portion are otherwise discarded, while decode decisions output by the decode portion are output as a decoded signal. In the next decode cycle, input previously provided to the decode portion is again provided to the history portion, in a sliding, overlapping block manner.

In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.

Methods and systems are described for sampling a data signal using a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor, measuring an eye opening of the data signal by adjusting a decision threshold of a spare sampler operating outside of the data signal processing path to determine a center-of-eye value for the decision threshold of the spare sampler, initializing the decision threshold of the spare sampler based on the center-of-eye value and the DFE correction factor, generating respective sets of phase-error signals for the spare sampler and the data sampler responsive to a detection of a predetermined data pattern, and updating the decision threshold of the data sampler based on an accumulation of differences in phase-error signals of the respective sets of phase-error signals.

A dynamic module and a decision feedback equalizer are provided. The decision feedback equalizer includes two dynamic modules, which have symmetric circuits and connections. The dynamic module includes a first domino circuit, a second domino circuit, and a storage circuit. In response to a first previous decision bit and a second previous decision bit, a first multiplexer output and a second multiplexer output are generated. The dynamic module alternatively operates in an evaluation period and a precharge period, depending on a clock signal. In the evaluation period, the first and the second multiplexer outputs are updated by the first domino circuit and the second domino circuit. In the precharge period, the first and the second multiplexer outputs are held by the storage circuit.

Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.

Decision feedback equalizers and equalization methods may employ fractional tap unrolling and/or probability-based decision threshold placement. One illustrative fractional tap unrolling equalization method embodiment includes: tracking preceding symbol decisions; converting an equalized signal into tentative symbol decisions with a precompensation unit; and selecting from the tentative symbol decisions based on the preceding symbol decisions. The precompensation unit has a decision element for each combination of a first number of speculative preceding symbols, with comparators in each decision element using a first type of symbol decision threshold that accounts for trailing intersymbol interference from the corresponding combination, and with an additional comparator in at least one of the decision elements using a second type of symbol decision threshold that accounts for trailing intersymbol interference from a second number of speculative preceding symbols, the second number being greater than the first.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.