Techniques are described for pre-equalization at the demodulator of a satellite receiver terminal to compensate for forward link distortions. Some satellite channel filters can manifest distortions, such as asymmetric group delay response. Such distortions can conventionally force restriction of symbol rate only to the portion of the channel bandwidth having a symmetric filter response. Embodiments include a pre-equalizer in the demodulation path that filters received downlink communications based on a set of pre-equalizer filter coefficients computed to at least partially compensate for the channel filter distortions. Some embodiments support updating the filter coefficients based on channel reassignments, and/or dynamically updating the filter coefficients based on detecting and exploiting pre-equalization frames. The pre-equalized sample stream can facilitate reliable decoding by the demodulator with an appreciably increased symbol rate and correspondingly increased forward link capacity.

System and method of timing recovery to achieve sampling phase optimization with aid of equalization adaptation. For equalizer filter, the offset between a current Center of Filter (COF) value and a nominal COF value is used as a measure for a clock phase correction resulted from an adaptive equalization process. A COF may be defined as a function of two selected tap weights or equal to a selected tap weight. The nominal COF value can be dynamically adapted based on the real-time sampling phase error. The tap weights of the equalizer filter are adjusted to decrease the offset, e.g., by interpolating/extrapolating selected tap weights based on the offset. By using sampling phase error as a feedback for COF_nom updating and so for equalization adaptation, the clock delay correction contributed by the adaptive equalization process is advantageously controlled to benefit sampling phase optimization.

The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.

An equalizer circuit includes a first adder circuit adding an input signal and including an addition terminal and a subtraction terminal; a comparator circuit comparing an output signal of the first adder circuit; a latch circuit latching data output from the comparator circuit; a first digital/analog converter circuit which outputs a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value; a second digital/analog converter circuit which outputs a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and a switch circuit which switches a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

A system for optimum phase searching in an Ethernet physical layer includes a time recovering circuit and an equalizer. The time recovering circuit includes a loop filter and a time error detector, and the equalizer includes a feed forward equalizer, a slicer and a feed backward equalizer. An optimum phase searching method includes obtaining optimum phases when mean squared errors calculated by the slicer are less than a first threshold, absolute values of mean values of outputs calculated by a time error detector are less than a second threshold, and the outputs are monotonic.

The present application relates to an adaptive filter using resource sharing and a method of operating the adaptive filter. The filter comprises at least one computational block, a monitoring block and an offset calculation block. The computational block is configured for adjusting a filter coefficient, c.sub.i(n), in an iterative procedure according to an adaptive convergence algorithm. The monitoring block is configured for monitoring the development of the determined filter coefficient, c.sub.i(n), during the performing of the iterative procedure. The offset calculation block is configured for determining an offset, Off.sub.i, based on a monitored change of the filter coefficient, c.sub.i(n), each first time period, T.sub.1, and for outputting the determined offset, Off.sub.i, to the computational block if the determined filter coefficient, c.sub.i(n), has not reached the steady state. The computational block is configured to accept the determined offset, Off.sub.i, and to inject the determined offset, Off.sub.i, into the iterative procedure.