A method of fabricating a semiconductor device, the method including forming a deposition active layer and a guide pattern on a semiconductor substrate such that the guide pattern delimits an exposed surface of the deposition active layer; and selectively depositing a metal-containing layer on the exposed surface of the deposition active layer exposed by the guide pattern, wherein the deposition active layer is a nonmetal layer.

Provided are an insulated gate bipolar transistor and a preparation method therefor. An auxiliary groove gate, namely a structure of an auxiliary groove, an auxiliary gate layer and the corresponding gate oxide layer, is arranged below an emitting metal electrode between a first common groove and a second common groove so as to provide a carrier pathway when the insulated gate bipolar transistor is turned off, so that not only the turn-off speed of the insulated gate bipolar transistor is increased, but also the reverse-biased safety operation area characteristic of the insulated gate bipolar transistor is improved, thus improving the performance of the insulated gate bipolar transistor.

Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. The metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition with process parameters selected so as to produce grains of material exhibiting a uniaxial grain orientation. The uniaxial grain structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

A resistor for dynamic random access memory includes a substrate with a memory cell region and a peripheral region defined thereon, and a resistor formed on a shallow trench isolation of the substrate, wherein the resistor is provided with a winding portion and terminal portions at two ends of the winding portion. The winding portion is electrically connected with an overlying metal layer through contacts, and the terminal portion includes a polysilicon layer and a metal multilayer from the bottom up.

A method of fabricating a semiconductor device is provided. A substrate is provided. The substrate includes a first region, a second region and a third region. An isolation structure is formed on the substrate in the first and the second region. A removing process is performed to remove the isolation structure in the first region, so as to form a first opening exposing a top surface of the substrate. A gate structure is formed on the substrate, covering a part of the substrate in the first region and a part of the isolation structure in the second region. A first doped region of a first conductive type is formed at one side of the gate structure in the first region, and a second doped region of the first conductive type is formed in the substrate in the third region.

In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

A semiconductor structure, such as a CMOS device, includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first composite gate electrode containing a first vertical stack of a p-doped semiconductor gate electrode, a first interfacial dielectric layer, and a first metallic gate electrode. The second field effect transistor includes a second composite gate electrode containing a second vertical stack that includes an n-doped semiconductor gate electrode and a second metallic gate electrode. A second interfacial dielectric layer having a second thickness that is thinner than the first interfacial dielectric layer may, or may not, be present in the second composite gate electrode.

Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.