A plating chuck for holding a substrate during plating processes, wherein the substrate has a notch area (3031) and a patterned region (3032) adjacent to the notch area (3031). The plating chuck comprises a cover plate (3033) configured to cover the notch area (3031) of the substrate to shield the electric field at the notch area (3031) when the substrate is being plated.

A copper interconnect with self-aligned hourglass-shaped metal cap comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a metal cap formed on top of each interconnect line of the plurality of interconnect lines, where the metal cap is formed with self-aligning concave sides extending from a top surface of the dielectric layer to a top surface of the metal cap.

A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.

A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

A method of depositing nitride films is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing nitride films which utilizes separate reaction and nitridation plasmas. In some embodiments, the nitride films have improved growth per cycle (GPC) relative to films deposited by thermal processes or plasma processes with only a single plasma exposure. In some embodiments, the nitride films have improved film quality relative to films deposited by thermal processes or plasma processes with only a single plasma exposure.

A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.

A method comprises forming a gate structure over a substrate; forming a gate helmet to cap the gate structure; forming a source/drain contact on the substrate; depositing a contact etch stop layer (CESL) over the gate helmet and the source/drain contacts, and an interlayer dielectric (ILD) layer over the CESL; performing a first etching process to form a gate contact opening extending through the ILD layer, the CESL and the gate helmet to the gate structure; forming a metal cap in the gate contact opening; with the metal cap in the gate contact opening, performing a second etching process to form a source/drain via opening extending through the ILD layer, the CESL to the source/drain contact; and after forming the source/drain via opening, forming a gate contact over the metal cap and a source/drain via over the source/drain contact.

The invention provides a process for the deposition of titanium silicon nitride (TiSiN) films onto a substrate, such as a substrate surface on a microelectronic device. Surprisingly, the process can be run at relatively low temperatures for the silicon precursors described herein.

A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.