Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl.sub.4), hydrogen (H.sub.2) and argon (Ar) in a region between a lid heater and a showerhead of a process chamber at a first temperature of 200 to 800 degrees C.; and flowing reaction products into the process chamber to selectively form a titanium material layer upon the silicon surface of the substrate.

Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.

A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI.sub.4) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 μΩ-cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.

An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.

Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.

A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.

Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

A method of manufacturing a semiconductor device includes: forming an amorphous metal film on a substrate by time-divisionally conducting a cycle a predetermined number of times, the cycle including: (a) simultaneously supplying a metal-containing gas and a first reducing gas to the substrate to form a first amorphous metal layer on the substrate, and (b) forming a second amorphous metal layer on the first amorphous metal layer by time-divisionally supplying, a predetermined number of times, the metal-containing gas and a second reducing gas to the substrate on which the first amorphous metal layer is formed; and forming a crystallized metal layer on the substrate by simultaneously supplying the metal-containing gas and the first reducing gas to the substrate on which the amorphous metal film is formed.