According to one embodiment of the present disclosure, there is provided a substrate processing method including: providing a substrate; forming a seed layer on a surface of the substrate by heating a stage on which the substrate is placed to a first temperature and supplying a first source gas to the substrate; and forming a metal-containing film by heating the stage on which the substrate is placed to a second temperature and supplying a second source gas and a first reducing gas to the substrate on which the seed layer is formed.

The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.

Aspects of this disclosure relate to selective removal of material of a layer, such as a carbon-containing layer. The layer can be over a patterned structure of two different materials. Treating the layer to cause the removal agent to be catalytically activated by a first area of the patterned structure to remove material of the organic material over the first area at a greater rate than over a second area of the patterned structure having a different composition from the first area.

Methods of depositing high purity metal films are discussed. Some embodiments utilize a method comprising exposing a substrate surface to an organometallic precursor comprising a metal selected from the group consisting of molybdenum (Mo), tungsten (W), osmium (Os), rhenium (Re), iridium (Ir), nickel (Ni) and ruthenium (Ru) and an iodine-containing reactant comprising a species having a formula RI.sub.x, where R is one or more of a C.sub.0-C.sub.10 alkyl, cycloalkyl, alkenyl, or alkynyl group and x is in a range of 1 to 4 to form a carbon-less iodine-containing metal film; and exposing the carbon-less iodine-containing metal film to a reductant to form a metal film. Some embodiments deposit a metal film with greater than or equal to 90% metal species on an atomic basis.

Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.

The present invention relates to a semiconductor device with improved reliability and a method for manufacturing the same. A semiconductor device according to the present invention may comprise: a substrate including a gate trench; a gate insulating layer formed on a surface of the gate trench; and silicon-doped metal nitride on the gate insulating layer, wherein the silicon-doped metal nitride has a silicon concentration of less than 1 at %.