Patent classifications
H01L21/28562
METHOD OF PROCESSING SUBSTRATE, RECORDING MEDIUM, SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
There is provided a technique that includes: (a) supplying a metal element-containing gas to a substrate accommodated in a process vessel; (b) supplying a reducing gas to the substrate; (c) performing (a) and (b) a predetermined number of times to form a film containing a metal element on the substrate; (d) supplying a modifying gas to the film to form a layer including an element contained in the modifying gas on a surface of the film after (c); and (e) creating a rare gas atmosphere in the process vessel and in a transfer chamber adjacent to the process vessel and carrying the substrate out of the process vessel and into the transfer chamber after (d).
FLUORINE-CONTAINING CONDUCTIVE FILMS
An atomic layer deposition (ALD) process for depositing a fluorine-containing thin film on a substrate can include a plurality of super-cycles. Each super-cycle may include a metal fluoride sub-cycle and a reducing sub-cycle. The metal fluoride sub-cycle may include contacting the substrate with a metal fluoride. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant.
Conformal and smooth titanium nitride layers and methods of forming the same
The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN). In one aspect, a method of forming a thin film comprising TiN comprises exposing a semiconductor substrate to one or more first cyclical vapor deposition cycles each comprising an exposure to a first Ti precursor and an exposure to a first N precursor to form a first portion of the thin film and exposing the semiconductor substrate to one or more second cyclical vapor deposition cycles each comprising an exposure to a second Ti precursor and an exposure to a second N precursor to form a second portion of the thin film, wherein exposures to one or both of the first Ti precursor and the first N precursor during the one or more first cyclical vapor deposition cycles are at different pressures relative to corresponding exposures to one or both of the second Ti precursor and the second N precursor during the one or more second cyclical vapor deposition cycles. Aspects are also directed to semiconductor structures incorporating the thin film and method of forming the same.
REACTANT GAS PULSE DELIVERY
Providing herein are methods of delivery of gas reactants to a processing chamber and related apparatus.
Cobalt deposition selectivity on copper and dielectrics
A process for forming cobalt on a substrate, comprising: volatilizing a cobalt precursor of the disclosure, to form, a precursor vapor: and contacting the precursor vapor with the substrate under vapor deposition conditions effective for depositing cobalt on the substrate from the precursor vapor, wherein the vapor deposition conditions include temperature not exceeding 200° C., wherein: the substrate includes copper surface and dielectric material, e.g., ultra-low dielectric material. Such cobalt deposition process can be used to manufacture product articles in which the deposited cobalt forms a capping layer, encapsulating layer, electrode, diffusion layer, or seed for electroplating of metal thereon, e.g., a semiconductor device, flat-panel, display, or solar panel. A cleaning composition containing base and oxidizing agent components may be employed to clean the copper prior to deposition of cobalt thereon, to achieve substantially reduced defects in the deposited cobalt.
Method Of Forming A Metal Liner For Interconnect Structures
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.
FILM FORMING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND FILM FORMING APPARATUS
A film forming method of forming a titanium silicide film in a contact forming region of a substrate includes: preparing the substrate having the contact forming region; and forming the titanium silicide film in the contact forming region of the substrate by atomic layer deposition (ALD) by sequentially supplying TiI.sub.4 gas as a Ti precursor and a Si-containing gas as a reducing gas to the substrate.
SELECTIVE BLOCKING OF METAL SURFACES USING BIFUNCTIONAL SELF-ASSEMBLED MONOLAYERS
Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups selected from alkene, alkyne, ketone, hydroxyl, aldehyde, or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.
METHOD AND APPARATUS FOR FILLING GAP USING ATOMIC LAYER DEPOSITION
A method and an apparatus for filling a gap by using an atomic layer deposition (ALD) method are provided. The method includes forming a first reaction inhibition layer on a side wall of the gap; forming a first precursor layer by adsorbing a first reactant into a bottom of the gap and the side wall of the gap around the bottom of the gap; and forming a first atomic layer on the bottom of the gap and the side wall of the gap around the bottom of the gap by adsorbing a second reactant into the first precursor layer. The forming of the first reaction inhibition layer may include adsorbing a first reaction inhibitor into the side wall of the gap; and forming a second reaction inhibitor by removing a specific ligand from the first reaction inhibitor.
Self-aligned contacts
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.