Patent classifications
H01L21/28593
Heterostructure field-effect transistor
Heterostructure field-effect transistor (HFET) having a channel layer, a barrier layer disposed on the channel layer, and a gate, source and drain electrodes disposed on the barrier layer, respectively, and corresponding fabrication methods are disclosed. The drain electrode includes a p-type semiconductor patterned structure and a raised drain section, the drain electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface together with a side surface of p-type semiconductor patterned structure and a bottom surface together with a side surface of raised drain section, the ohmic contact is formed between another surface of raised drain section and barrier layer, the raised drain section partially surrounding the p-type semiconductor patterned structure, and a bandgap of the channel layer is less than a bandgap of the barrier layer.
SEMICONDUCTOR DEVICE
A semiconductor structure includes a substrate, a semiconductor stack, a cap layer, a source electrode, a drain electrode, and a gate. The semiconductor stack is disposed on the substrate. The cap layer is disposed on the semiconductor stack. The cap layer includes an intrinsic cap layer, an etch-stop layer, and an n-type cap layer. There is an opening through the cap layer. The source electrode and the drain electrode are disposed on the semiconductor stack. The gate is disposed in the opening and between the source electrode and the drain electrode. The first distance between the gate and a first portion of the n-type cap layer adjacent to the drain electrode is greater than the second distance between the gate and a second portion of the n-type cap layer adjacent to the source electrode.