A semiconductor device includes a plurality of wire bonds formed on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; a protective material is applied around the plurality of wire bonds, the protective material having a first pH; and at least a portion of the semiconductor device and the protective material are encapsulated with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.

A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.

As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

A bonding wire for a high-speed signal line for connecting a pad electrode of a semiconductor device and a lead electrode on a circuit board contains palladium (Pd), platinum (Pt), silver (Ag), and a trace additive element.

A bonding wire for a high-speed signal line for connecting a pad electrode of a semiconductor device and a lead electrode on a circuit board contains palladium (Pd), platinum (Pt), silver (Ag), and a trace additive element.

A wire, preferably a bonding wire for bonding in microelectronics, contains a copper core with a surface and coating layer containing aluminum superimposed over the surface of the copper core. The ratio of the thickness of the coating layer to the diameter of the copper core is from 0.05 to 0.2 m. The wire has a diameter in the range of from 100 m to 600 m and specified standard deviations of the diameter of the copper core and of the thickness of the coating layer. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing at least two elements and the wire, to a propelled device containing the electric device, and to a process of connecting two elements through the wire by wedge bonding.

A wire, preferably a bonding wire for bonding in microelectronics, contains a copper core with a surface and coating layer containing aluminum superimposed over the surface of the copper core. The ratio of the thickness of the coating layer to the diameter of the copper core is from 0.05 to 0.2 m. The wire has a diameter in the range of from 100 m to 600 m and specified standard deviations of the diameter of the copper core and of the thickness of the coating layer. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing at least two elements and the wire, to a propelled device containing the electric device, and to a process of connecting two elements through the wire by wedge bonding.

A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.