H01L21/32138

METHOD FOR PRODUCING PLASTIC ELEMENT PROVIDED WITH FINE SURFACE ROUGHNESS
20220013369 · 2022-01-13 · ·

A method for producing a plastic element provided with fine surface roughness is provided. In the method, etching of a surface of the plastic element is performed separately in a first step and in a second step, in the first step, fine roughness having a predetermined average value of pitch in the range from 0.05 to 1 micrometer is generated on the surface through reactive ion etching in an atmosphere of a first gas; and in the second step, an average value of depth of the fine roughness generated in the first step is adjusted to a predetermined value in the range from 0.15 to 1.5 micrometers while the predetermined average value of pitch is substantially maintained through reactive ion etching in an atmosphere of a second gas, reactivity to the plastic element of the second gas being lower than reactivity to the plastic element of the first gas.

Abatement and strip process chamber in a dual loadlock configuration

Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume.

Abatement and strip process chamber in a dual load lock configuration

Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume.

Semiconductor arrangement and method of manufacture

A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer.

ELECTRON EXCITATION ATOMIC LAYER ETCH
20230298904 · 2023-09-21 ·

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

TREATMENT LIQUID AND SUBSTRATE TREATMENT METHOD

An object of the present invention to provide a treatment liquid for a semiconductor device, where the treatment liquid has an excellent corrosion prevention property with respect to a metal-containing layer and excellent removability of an object to be removed, and also has excellent solubility in a post-treatment liquid. In addition, an object of the present invention is to provide a substrate treatment method using the treatment liquid.

The treatment liquid of the present invention is a treatment liquid for a semiconductor device, which contains water, a removing agent, and a copolymer, and the copolymer has a first repeating unit having at least one group selected from the group consisting of a primary amino group, a secondary amino group, a tertiary amino group, and a quaternary ammonium cation, and a second repeating unit different from the first repeating unit.

METAL DEPOSITION AND ETCH IN HIGH ASPECT-RATIO FEATURES

Exemplary methods of etching may include flowing a fluorine-containing precursor and a secondary gas into a processing region of a semiconductor processing chamber. The secondary gas may be or include oxygen or nitrogen. A flow rate ratio of the fluorine-containing precursor to the secondary gas may be greater than or about 1:1. The methods may include contacting a substrate with the fluorine-containing precursor and the secondary gas. The substrate may include an exposed metal. The substrate may define a high aspect-ratio structure. The methods may include etching the exposed metal within the high aspect-ratio structure.

Semiconductor device manufacturing method

A semiconductor device manufacturing method includes the steps of etching a semiconductor material by using plasma, forming a damage layer on the semiconductor material, and removing the damage layer such that a relatively low temperature process can form a fine pattern with a vertical cross section using a compound semiconductor material or the like.

METHOD OF FABRICATING CONTACT STRUCTURE

A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES

Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.