Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/04
Structure, shape, material or disposition of the bonding areas prior to the connecting process
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H01L2224/05
of an individual bonding area
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H01L2224/05085
with additional elements, e.g. vias arrays, interposed between the stacked layers
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H01L2224/05089
Disposition of the additional element
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H01L2224/05091
at the center of the internal layers
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H01L2224/05091

Semiconductor structure including hybrid bond contact and manufacturing method thereof
20250349765 · 2025-11-13 · ·

The present invention provides a semiconductor structure containing a hybrid bond contact, comprising a first hybrid bond contact located in a dielectric layer. The first hybrid bond contact is consisting of copper. A first top wiring layer is situated within the dielectric layer and below the first hybrid bond contact, wherein the first top wiring layer is made of aluminum. A first composite liner layer is positioned between the first hybrid bond contact and the first top wiring layer. From a cross-sectional view, the first composite liner layer encapsulates the sidewalls and bottom surface of the first hybrid bond contact. The first composite liner layer consists of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer.