Patent classifications
Y02D30/50
Faulty multi-layer link restoration method and controller
In a troubleshooting method, a controller first determines that a fault occurs on a first multi-layer link passing through a first port on a first network device, where the first multi-layer link is a link in a link aggregation group between the first network device and a second network device. The controller then releases an optical layer resource of the first multi-layer link, and deletes the first multi-layer link from the link aggregation group. The controller further establishes, a second multi-layer link for restoration of the first multi-layer link, based on a first idle port on the first network device and a second idle port on a target network device, and adds the second multi-layer link to a target link aggregation group between the first network device and the target network device.
Buffer management during power state transitions using self-refresh and dump modes
A storage device includes a non-volatile memory including a plurality of non-volatile memory cells, a buffer memory configured to temporarily store write data to be written to the non-volatile memory or read data read from the non-volatile memory, and a controller configured to receive a sleep mode signal from an external host. When the sleep mode signal is received by the controller, the controller is configured to block a first power supplied to the non-volatile memory and set the buffer memory to one of a first mode in which a second power is blocked from being supplied to the buffer memory and a second mode in which the buffer memory operates with low power. The write data stored in the buffer memory is written to the non-volatile memory when the buffer memory is set to the first mode.
Fault tolerant and load balanced routing
Techniques are described for balancing traffic load for networks configured in multi-rooted tree topologies, in the presence of link failures. Maximum flows (through minimum cuts) are calculated for subgraphs that incorporate effective link capacities on links between source and destination nodes. Effective link capacities may be determined that take into account link failures, as well as sharing of current available link capacities by multiple nodes. Traffic is balanced while simultaneously fully utilizing available link capacities, even available link capacities on partially failed links (e.g., partially failed Link Aggregation Groups (LAGs)).
Electronic device and control method therefor
An example electronic apparatus includes a communication circuitry; a power supply; a first processor configured to have a first mode which receives first power from the power supply and connects with a server through the communication circuitry to transmit and receive information, and a second mode which receives no power or second power lower than the first power from the power supply; and a second processor configured to repetitively output a mode switching signal within a preset range of time interval based on the second mode of the first processor, wherein the first processor is switched over to the first mode based on the mode switching signal, is configured to transmit connectivity keeping information to the server through the communication circuitry and is switched over to the second mode.
Electronic system, corresponding method of operation and electronic device
An embodiment electronic system comprises a first device, a second device and a clock generator circuit. The clock generator circuit is configured to provide a clock signal having a selectable frequency. The first device comprises a first processing circuit having coupled therewith a first Ethernet interface, and the second electronic device comprises a second processing circuit having coupled therewith a second Ethernet interface. At least one of the first device and the second device is configured to determine a frequency of the clock signal as a function of an operating parameter of the first device and/or of the second device and/or as a function of a parameter of the frames exchanged between the first device and the second device, and to act on the clock generator circuit to operate the clock generator circuit at the frequency.
Recommendation generation based on selection of selectable elements of visual representation
Some embodiments provide a novel method for collecting and reporting attributes of data flows associated with machines executing on a plurality of host computers to an analysis appliance and providing visual representations of the data to a user. Some embodiments provide a visual representation of the collected data that allows a user to select a set of machines and flows and initiate recommendation generation based on the selected machines and flows. The recommendation generation, in some embodiments, includes identifying flows for which rules have not been defined and filtering the identified rules to remove flows for which rules should not be defined. Some embodiments use the identified rues to identify services and groups associated with the rules and generate recommendations for rules, groups and services based on the identified flows, groups and services. The recommendations, in some embodiments, are implemented as a single PATCH API.
AUTOMATIC LINK AGGREGATION FOR INCOMPATIBLE DATA PORTS ON A COMPUTER NETWORK
An aggregate port selection is received from user to bundle at least two individual data ports of the network device for single channel data transfer. The lowest common denominators of physical capabilities (speed and duplex) of selected ports on the network device is determined through an operating system. Downgraded physical capabilities of at least one of the at least two data ports are committed to match lowest common denominators of the at least two data ports. Data exchanges are conducted over the at least two ports of the network device according to LACP.
Method of operating semiconductor device
System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal based on first control signal, and memory interface clock circuit sets clock rate of memory interface clock signal based on second control signal.
Link aggregation with receive side buffering
The present disclosure relates to a communication arrangement (110, 130) adapted for link aggregation of a plurality of communication links (120a, 12b, 120c). The communication arrangement (110, 130) is adapted to communicate via the plurality of communication links (120a, 120b, 120c) and comprises a traffic handling unit (112, 132) that is adapted to obtain data segments (414-417, 419-421, 423-425) to be transmitted, and to identify one or more data flows (401, 402, 403, 404) in said data segments. The traffic handling unit is adapted to attach sequence numbers, SEQ, to data segments associated with each identified data flow (401, 402, 403, 404), wherein sequence numbers are independent between data flows and to select a communication link for transmission of a data segment associated with a certain data flow (401, 402, 403, 404). The selecting comprises selecting a previous communication link that has been used for transmission of a previous data segment from said certain data flow (401, 402, 403, 404) if possible, and selecting any communication link otherwise.
Method, system, and device for data flow metric adjustment based on communication link state
Embodiments of this application provide a network optimization method, a network optimization system, and a network device, and relate to the communications field. A first network device adjusts, if it is detected that a communications link between the first network device and a second network device is in an abnormal state, a metric of at least one data flow received by the first network device; and the first network device selects a transmission path for the at least one data flow based on adjusted metric, and transmits the at least one data flow to the selected transmission path. In this way, load of the communications link is reduced, and the communications link is restored to a normal state.