The present disclosure is directed to a wafer container including: a housing configured for transporting a plurality of wafers, wherein the plurality of wafers are stacked on a base of the housing in a first direction; a plurality of wafer separator rings; each of the wafer separator rings configured to encircle a wafer of the plurality of wafers in a second direction that is substantially perpendicular to the first direction, each of the wafer separator rings including a top surface and a bottom surface, defining a thickness there between extending in the first direction, which is about 0.3 mm-1.4 mm; and each of the wafer separator rings including an inner side wall and an outer side wall defined by an inner diameter and an outer diameter, respectively, in the second direction, wherein the inner diameter of the wafer separator ring is greater than 300 mm and configured to be spaced apart from the wafer it is encircling.

A method for manufacturing a rotor shaft for an electrical aggregate, including providing a pin having a shaft plug-in, in particular a cylindrical shaft plug-in; producing a hollow rotor shaft body being open at least at a first end for receiving the pin and in form of a rotary body, where an oversize exists between at least one outer surface of the shaft plug-in and at least one inner surface of the rotor shaft body; and inserting the shaft plug-in into the rotor shaft body for fastening the pin to the rotor shaft body for finishing the rotor shaft, such that the process and operation of manufacturing a rotor shaft is simplified while at the same time reducing costs and material waste, and to produce a rotor shaft that can withstand high loads and transmit high torques.

A tape sectioning system, comprising a tape web feed path for feeding a web of fiber reinforced tape, a quality inspection system arranged along the web feed path that inspects the quality of the web of tape, and a sectioner that sections off longitudinal tape sections from the web of tape, wherein the sectioner is arranged to vary the length of the tape sections that are sectioned off from the web of tape based on the outcome of the quality inspection.

Embodiments are described herein that apply capping layers to cores prior to spacer formation in self-aligned multiple patterning (SAMP) processes to achieve vertical spacer profiles. For one embodiment, a plasma process is used to deposit a capping layer on cores, and this capping layer causes resulting core profiles to have protective caps. These protective caps formed with the additional capping layer help to reduce or minimize material loss and corner loss of the core material during spacer deposition and spacer etch processes. This reduction in core material loss improves the resulting spacer profile so that a more vertical profile is achieved. For one embodiment, an angle of 80-90 degrees is achieved for vertical sidewalls of the spacers adjacent core sites with respect to the horizontal surface of the underlying layer, such as a hard mask layer formed on a substrate for a microelectronic workpiece.

Embodiments disclosed herein generally relate to methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a III-V epitaxial growth process or an etch clean process, and prior to additional processing. An oxygen containing gas is flowed to a substrate in a load lock chamber, and subsequently a non-reactive gas is flowed to the substrate in the load lock chamber. As such, hazardous gases and outgassing residuals are decreased and/or removed from the substrate such that further processing may be performed.

Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes first and second layers that each have one or more electronic components. One or more electronic components of each layer can be electrically connected by a first via and a second via. The integrated circuit also includes an isolation cell operatively connected between the first via and the second via. The isolation cell is configured to controllably break electrical connection between the first via and the second via subsequent to testing of the at least one electronic component of the second layer. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops.

In one embodiment, an electric machine is provided. The electric machine includes a machine housing and a stator disposed at least partially within the housing, the stator comprising a plurality of teeth and an aluminum winding wound around at least one tooth of the plurality of teeth. The electric machine further includes a radially embedded permanent magnet rotor disposed at least partially within the housing, the rotor comprising at least one radially embedded permanent magnet and configured to provide increased flux to reduce motor efficiency loss compared to a copper winding.

A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail.

A method of progressive processing includes feeding a strip-shaped sheet to a press machine; pressing the strip-shaped sheet with the press machine; and joining the strip-shaped sheet with a new strip-shaped sheet by applying a tape over an end of the strip-shaped sheet located in a direction opposite a direction in which the strip-shaped sheet is fed and an end of the new strip-shaped sheet located in a direction in which the new strip-shaped sheet is fed.

A semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. A barrier layer on the sidewalls of the trench is formed using a surface modification process and a surface treatment process.