A plasma cutting system for measuring or monitoring the voltage between a plasma torch and the material being cut to determine a voltage or voltage signature and comparing that measurement against predetermined values to indicate that an initial pierce of the material is complete, and based on the measurement, moving the torch or the material to a different location for additional cutting. The system further provides a Fix Drawing Tool, which will automatically detect and fix gaps or overlaps in a drawing that are very difficult to find visually. These gaps and overlaps become a problem when trying to make a proper toolpath because a CAM program requires a clean, closed shape. The system also provides a Dynamic Corner Looping system, which automatically adjusts with the feed-rate and accelerations of the toolpath and plasma machine, eliminates unwanted dross, sharpens corners and minimizes material loss. A pendant tethering system is also disclosed for managing control of a CNC machine remotely. Additional disclosed functionality includes a data collection system, a manual hand wheel with 3D simulation and a multiple fabrication head management system.

An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises: a base substrate (1), thin-film transistors (TFTs), an isolation layer (10) and an organic resin layer (8) formed on the base substrate (1), and a common electrode layer (12) formed on the organic resin layer (8). The isolation layer (10) covers source electrodes (6) and drain electrodes (7) of the TFTs; the organic resin layer (8) covers the isolation layer (10) and is provided with first through holes (9) corresponding to the drain electrodes (7) of the TFTs; the isolation layer (10) is provided with second through holes (11) communicated with the first through holes (9) to expose partial drain electrodes (7); and the dimension of the second through holes (11) is greater than that of the first through holes (9). The array substrate, the manufacturing method thereof and the display device resolve the problem of forming dark dots, ensure the product quality, reduce the waste of production materials, and reduce the production cost.

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

A heterogeneous composite material and a method for manufacturing the heterogeneous composite material are provided. The heterogeneous composite material includes a first compression structure formed by compressing a first material, and a second compression structure formed by compressing a second material different from the first material, and disposed in close contact with the first compression structure, wherein at least a portion of the first compression structure and at least a portion of the second compression structure are disposed on both sides of a boundary surface existing in a circular shape with a predetermined radius with respect to a central axis in a state in contact with each other at the boundary surface.

A semiconductor device is disclosed including a gate electrode structure and raised drain and source regions that extend to a first height level and a sidewall spacer element positioned adjacent the sidewalls of the gate electrode structure between the raised drain and source regions and the gate electrode structure. The sidewall spacer element includes an upper portion that extends above the first height level wherein an inner part of the spacer element faces the gate electrode structure and extends to a second height level that is less than a third height level of an outer part of the upper portion of the spacer element.

A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.

Interconnected substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages for fabricating microelectronic packages utilizing interconnected substrate arrays containing integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnected substrate array having an integrated ESD protection grid. The ESD protection grid includes, in turn, ESD grid lines at least partially formed in singulation streets of an interconnected substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level fabrication steps are performed to produce an interconnected package array utilizing the interconnected substrate array, while electrically coupling the die attachment regions to electrical ground through the ESD protection grid during at least one of the array-level fabrication steps. Afterwards, the interconnected package array is singulated to yield a plurality of singulated microelectronic packages.

A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.

A CNT dispersion includes a dispersion medium, and a nanocarbon material containing carbon nanotubes dispersed in the dispersion medium. 98% or more of the nanocarbon material has a length of 1 μm or more and 105 μm or less and the nanocarbon material has an average aspect ratio of 100 or more and 20000 or less.

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.