A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. The first transistor is arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device also includes a first conductive line arranged in a third layer between the first layer and the second layer and extending in the second direction, wherein the first conductive line is configured to electrically connect a first source/drain region of the first active region to a second source/drain region of the second active region.

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.

The invention discloses a method for cutting a substrate wafer from an indium phosphide crystal, and belongs to the field of semiconductor substrate preparation, comprises the following steps of: 1) orientating, cutting the head and the tail of a crystal bar, adjusting the orientation and trying to cut the crystal bar until a wafer with a required crystal orientation cut, wherein the cutting end face is an orientation end face; 2) multi-wire cutting, on a multi-wire cutting apparatus, dividing a crystal bar parallel to an orientation end face into wafers; 3) cleaning, cleaning the wafer until no residue and no dirt existing on the surface; 4) circle cutting, performing circle cutting on the wafer to cut the desired crystal orientation area. According to the technical scheme, for the indium phosphide crystal bar which is difficult to control in diameter and easy to twinning/ poly in the growth process, a barreling process which may grind and remove a large amount of InP materials is abandoned, the crystal bar is multi-wire cut into a wafer, and then the substrate wafer which is available in the crystal direction close to the standard size is cut from the wafer to the maximum extent, so that the wafer output can be greatly increased, and the material loss and the waste can be reduced.

A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail.

A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

A closed-loop adaptive material deposition apparatus and method uses a scanning system to monitor an additively manufactured object as it is being fabricated and adapting the geometric shape and material composition of the subsequent layers based on the scan data. The scanning system repeatedly captures geometric and/or material information of a partially manufactured object with optional auxiliary objects inserted during the manufacturing process. Based on this information, the actual surface geometry and/or actual material composition is computed. Surface geometry may be offset and used as a slicing surface for the next portion of the digital model. The shape of the slicing surface may then be recomputed each time the system scans the partially fabricated object.

A method for manufacturing a rotor shaft for an electrical aggregate, including providing a pin having a shaft plug-in, in particular a cylindrical shaft plug-in; producing a hollow rotor shaft body being open at least at a first end for receiving the pin and in form of a rotary body, where an oversize exists between at least one outer surface of the shaft plug-in and at least one inner surface of the rotor shaft body; and inserting the shaft plug-in into the rotor shaft body for fastening the pin to the rotor shaft body for finishing the rotor shaft, such that the process and operation of manufacturing a rotor shaft is simplified while at the same time reducing costs and material waste, and to produce a rotor shaft that can withstand high loads and transmit high torques.

The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.