Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Disclosed is a photodiode, which includes a graphene-silicon quantum dot hybrid structure, having improved optical and electrical characteristics by controlling the sizes of silicon quantum dots and the doping concentration of graphene. The photodiode including the graphene-silicon quantum dot hybrid structure of the present disclosure may be easily manufactured, may be manufactured over a large area, has a wide photodetection band from the ultraviolet light region to the near infrared region, and allows selective absorption energy control.

An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and the electrically conductive feed line, a second substrate on the insulating layer, and an antenna on the second substrate and having nanofilm layers stacked on the second substrate. The antenna is coupled to the feed line through an aperture.

Discrete microstructures of predefined size and shape are prepared using sol-gel phase-reversible hydrogel templates. An aqueous solution of hydrogel-forming material is covered onto a microfabricated silicon wafer master template having predefined microfeatures, such as pillars. A hydrogel template is formed, usually by lowering the temperature, and the formed hydrogel template is peeled away from the silicon master template. The wells of predefined size and shape on the hydrogel template are filled with a solution or a paste of a water-insoluble polymer, and the solvent is removed to form solid structures. The formed microstructures are released from the hydrogel template by simply melting the hydrogel template in water. The microstructures are collected by centrifugation. The microstructures fabricated by this method exhibit pre-defined size and shape that exactly correspond to the microwells of the hydrogel template. The method of preparing microstructures based on hydrogel templates is simple and can easily produce large quantities of the microstructures.

Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.

Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

A method for forming electrical contacts for a solar cell and a solar cell formed using the method is provided. The method includes forming a first metal layer over predefined portions of a surface of the solar cell; depositing a carbon nanotube layer over the first metal layer; and forming a second metal layer over the carbon nanotube layer, wherein the first metal layer, the carbon nanotube layer, and the second metal layer form a first metal matrix composite layer that provides electrical conductivity and mechanical support for the metal contacts.

A polarizer that includes a substrate, and a metal grating formed on the substrate that includes a metal nano-wire array arranged in a predetermined direction.

A graphene oxide-coated graphitic foil, composed of a graphitic substrate or core layer having two opposed primary surfaces and at least a graphene oxide coating layer deposited on at least one of the two primary surfaces, wherein the graphitic substrate layer has a thickness preferably from 0.34 nm to 1 mm, and the graphene oxide coating layer has a thickness preferably from 0.5 nm to 1 mm and an oxygen content of 0.01%-40% by weight based on the total graphene oxide weight. The graphitic substrate layer may be preferably selected from flexible graphite foil, graphene film, graphene paper, graphite particle paper, carbon-carbon composite film, carbon nanofiber paper, or carbon nanotube paper. This graphene oxide-coated laminate exhibits a combination of exceptional thermal conductivity, electrical conductivity, mechanical strength, surface smoothness, surface hardness, and scratch resistance unmatched by any thin-film material of comparable thickness range.