Y10S977/943

Iron-based oxide magnetic particle powder and method for producing iron-based oxide magnetic particle powder

An e-type iron-based oxide magnetic particle powder has narrow particle size distribution and has a low content of fine particles which do not contribute to magnetic recording characteristics. As a result, a narrow coercive force distribution is achieved and the powder is suitable for increasing recording density of a magnetic recording medium. The powder containing substituting metal elements can be obtained by: adding an alkali to an aqueous solution containing trivalent iron ions and ions of the metals for partially substituting Fe sites to neutralize the aqueous solution to a pH of 1.5 to 2.5; then adding a hydroxycarboxylic acid; further adding the alkali to neutralize the aqueous solution to a pH of 8.0 to 9.0; washing with water a precipitation of an iron oxyhydroxide containing the substituting metal elements produced; and coating the iron oxyhydroxide containing the substituting metal elements with a silicon oxide and heating the resultant.

Nanoscale Device Comprising an Elongated Crystalline Nanostructure

The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

Method of synthesizing magnetite/maghemite core/shell nanoparticles

The method of synthesizing magnetite/maghemite core/shell nanoparticles is a modified co-precipitation method for producing iron oxide (Fe.sub.3O.sub.4/-Fe.sub.2O.sub.3) nanoparticles that allows for production of the Fe.sub.3O.sub.4/-Fe.sub.2O.sub.3 core/shell nanoparticles with a desired shell thickness ranging between about 1 nm to 5 nm for biomedical and data storage applications. Aqueous solutions of ferric and ferrous salts are mixed at room temperature and pH of the mixture is raised to 10. The mixture is then heated at 80 C. for different lengths of time at atmospheric pressure to adjust particle size, and the precipitate is dried at 120 C. in vacuum. Oxidation in an oxygen atmosphere for different lengths of time is used to adjust the thickness of the -Fe.sub.2O.sub.3 shell.

Nonvolatile Nanotube Memory Arrays using Nonvolatile Nanotube Blocks and Cell Selection Transistors

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Systems and methods for fabrication of superconducting integrated circuits

Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

Semiconductor Josephson Junction and a Transmon Qubit Related Thereto

The present disclosure relates to semiconductor based Josephson junctions and their applications within the field of quantum computing, in particular a tuneable Josephson junction device has been used to construct a gateable transmon qubit. One embodiment relates to a Josephson junction comprising an elongated hybrid nanostructure comprising superconductor and semiconductor materials and a weak link, wherein the weak link is formed by a semiconductor segment of the elongated hybrid nanostructure wherein the superconductor material has been removed to provide a semiconductor weak link.

Low power embedded one-time programmable (OTP) structures

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

Nanoscale device comprising an elongated crystalline nanostructure

The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

MEMORY CELLS HAVING ELECTRICALLY CONDUCTIVE NANODOTS AND APPARATUS HAVING SUCH MEMORY CELLS
20190214472 · 2019-07-11 · ·

Memory cells having a plurality of electrically conductive nanodots between a charge storage material and a dielectric, and apparatus having such memory cells, may facilitate non-volatile storage of data. The electrically conductive nanodots may be in contact with a surface of either the charge storage material, or a barrier material between the electrically conductive nanodots and the charge storage material.

Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.