A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

A device includes an upper metallic layer, a lower layer, and a memory array positioned between the upper and lower layers, wherein the memory electrical characteristic changes when storing data.

A device includes an upper metallic layer, a lower layer, and a nano sensor array positioned between the upper and lower layers to detect a presence of a gas, a chemical, or a biological object, wherein each sensor's electrical characteristic changes when encountering the gas, chemical or biological object.

The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.

In order to obtain a carbon nanotube array including no m-CNTs through simple steps using a mechanism that is different from thermocapillary flow, there are provided a process for producing a carbon nanotube array including (A) a step of preparing a carbon nanotube array in which m-CNTs and s-CNTs are horizontally aligned; (B) a step of forming an organic layer on the carbon nanotube array; (C) a step of applying voltage to the carbon nanotube array in a long axis direction of the carbon nanotubes constituting the carbon nanotube array in the air; and (D) a step of removing the organic layer, and a carbon nanotube array obtained by the process.

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising N.sub.w nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets N.sub.W, width W.sub.W,i, of the nanowire/nanosheet number i, i being an integer from 1 to N.sub.W, thickness of the nanowire/nanosheet H.sub.W,i, number i, i being an integer from 1 to N.sub.W, corner radius R.sub.W,i of the nanowire/nanosheet number i, i being an integer from 1 to N.sub.W, R.sub.W,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage .sub.T given by .sub.T=k.sub.BT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.

The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.